Low-power optimization by smart bit-width allocation in a systemC-based ASIC design environment

Arindam Mallik; Debjit Sinha; Prithviraj Banerjee; Hai Zhou

doi:10.1109/TCAD.2006.888291

Low-power optimization by smart bit-width allocation in a systemC-based ASIC design environment

Arindam Mallik^*, Debjit Sinha, Prithviraj Banerjee, Hai Zhou

^*Corresponding author for this work

Electrical and Computer Engineering

Research output: Contribution to journal › Article › peer-review

25 Scopus citations

Abstract

The modern era of embedded system design is geared toward the design of low-power systems. One way to reduce power in an application-specified integrated circuit (ASIC) implementation is to reduce the bit-width precision of its computation units. This paper describes algorithms to optimize the bit widths of fixed-point variables for low power in a SystemC-based ASIC design environment. We propose an optimal bit-width allocation algorithm for two variables and a greedy heuristic that works for any number of variables. The algorithms are used in the automation of converting floating-point SystemC programs into ASIC synthesizable SystemC programs. Expected inputs are profiled to estimate errors in the finite precision conversions. Experimental results for the tradeoffs between quantization error, power consumption, and hardware resources used are reported on a set of four SystemC benchmarks that are mapped onto a 0.18-μm ASIC cell library from Artisan Components. We demonstrate that it is possible to reduce the power consumption by 50% on the average by allowing roundoff errors to increase from 0.5% to 1 %.

Original language	English (US)
Pages (from-to)	447-454
Number of pages	8
Journal	IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume	26
Issue number	3
DOIs	https://doi.org/10.1109/TCAD.2006.888291
State	Published - Mar 2007

Funding

Dr. Zhou has served on the technical program committees of many conferences on very large scale integrated circuits and computer-aided design. He was the recipient of the CAREER Award from the National Science Foundation in 2003. Manuscript received April 3, 2006; revised August 11, 2006 and September 27, 2006. This work was supported in part by the National Aeronautics Space Administration (NASA) under Grant 276685 and in part by the Defense Advanced Research Projects Agency (DARPA) under Grant F33615-01-C-1631. This paper was recommended by Guest Editor D. Sciuto.

Keywords

Fixed-point arithmetic
High-level synthesis
Low-power design
Quantization

ASJC Scopus subject areas

Software
Computer Graphics and Computer-Aided Design
Electrical and Electronic Engineering

Access to Document

10.1109/TCAD.2006.888291

Cite this

@article{e7fd00e82dce4681817b5cedc84fec21,

title = "Low-power optimization by smart bit-width allocation in a systemC-based ASIC design environment",

abstract = "The modern era of embedded system design is geared toward the design of low-power systems. One way to reduce power in an application-specified integrated circuit (ASIC) implementation is to reduce the bit-width precision of its computation units. This paper describes algorithms to optimize the bit widths of fixed-point variables for low power in a SystemC-based ASIC design environment. We propose an optimal bit-width allocation algorithm for two variables and a greedy heuristic that works for any number of variables. The algorithms are used in the automation of converting floating-point SystemC programs into ASIC synthesizable SystemC programs. Expected inputs are profiled to estimate errors in the finite precision conversions. Experimental results for the tradeoffs between quantization error, power consumption, and hardware resources used are reported on a set of four SystemC benchmarks that are mapped onto a 0.18-μm ASIC cell library from Artisan Components. We demonstrate that it is possible to reduce the power consumption by 50% on the average by allowing roundoff errors to increase from 0.5% to 1 %.",

keywords = "Fixed-point arithmetic, High-level synthesis, Low-power design, Quantization",

author = "Arindam Mallik and Debjit Sinha and Prithviraj Banerjee and Hai Zhou",

note = "Funding Information: Dr. Zhou has served on the technical program committees of many conferences on very large scale integrated circuits and computer-aided design. He was the recipient of the CAREER Award from the National Science Foundation in 2003. Funding Information: Manuscript received April 3, 2006; revised August 11, 2006 and September 27, 2006. This work was supported in part by the National Aeronautics Space Administration (NASA) under Grant 276685 and in part by the Defense Advanced Research Projects Agency (DARPA) under Grant F33615-01-C-1631. This paper was recommended by Guest Editor D. Sciuto.",

year = "2007",

month = mar,

doi = "10.1109/TCAD.2006.888291",

language = "English (US)",

volume = "26",

pages = "447--454",

journal = "IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems",

issn = "0278-0070",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "3",

}

TY - JOUR

T1 - Low-power optimization by smart bit-width allocation in a systemC-based ASIC design environment

AU - Mallik, Arindam

AU - Sinha, Debjit

AU - Banerjee, Prithviraj

AU - Zhou, Hai

N1 - Funding Information: Dr. Zhou has served on the technical program committees of many conferences on very large scale integrated circuits and computer-aided design. He was the recipient of the CAREER Award from the National Science Foundation in 2003. Funding Information: Manuscript received April 3, 2006; revised August 11, 2006 and September 27, 2006. This work was supported in part by the National Aeronautics Space Administration (NASA) under Grant 276685 and in part by the Defense Advanced Research Projects Agency (DARPA) under Grant F33615-01-C-1631. This paper was recommended by Guest Editor D. Sciuto.

PY - 2007/3

Y1 - 2007/3

N2 - The modern era of embedded system design is geared toward the design of low-power systems. One way to reduce power in an application-specified integrated circuit (ASIC) implementation is to reduce the bit-width precision of its computation units. This paper describes algorithms to optimize the bit widths of fixed-point variables for low power in a SystemC-based ASIC design environment. We propose an optimal bit-width allocation algorithm for two variables and a greedy heuristic that works for any number of variables. The algorithms are used in the automation of converting floating-point SystemC programs into ASIC synthesizable SystemC programs. Expected inputs are profiled to estimate errors in the finite precision conversions. Experimental results for the tradeoffs between quantization error, power consumption, and hardware resources used are reported on a set of four SystemC benchmarks that are mapped onto a 0.18-μm ASIC cell library from Artisan Components. We demonstrate that it is possible to reduce the power consumption by 50% on the average by allowing roundoff errors to increase from 0.5% to 1 %.

AB - The modern era of embedded system design is geared toward the design of low-power systems. One way to reduce power in an application-specified integrated circuit (ASIC) implementation is to reduce the bit-width precision of its computation units. This paper describes algorithms to optimize the bit widths of fixed-point variables for low power in a SystemC-based ASIC design environment. We propose an optimal bit-width allocation algorithm for two variables and a greedy heuristic that works for any number of variables. The algorithms are used in the automation of converting floating-point SystemC programs into ASIC synthesizable SystemC programs. Expected inputs are profiled to estimate errors in the finite precision conversions. Experimental results for the tradeoffs between quantization error, power consumption, and hardware resources used are reported on a set of four SystemC benchmarks that are mapped onto a 0.18-μm ASIC cell library from Artisan Components. We demonstrate that it is possible to reduce the power consumption by 50% on the average by allowing roundoff errors to increase from 0.5% to 1 %.

KW - Fixed-point arithmetic

KW - High-level synthesis

KW - Low-power design

KW - Quantization

UR - http://www.scopus.com/inward/record.url?scp=33847701654&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=33847701654&partnerID=8YFLogxK

U2 - 10.1109/TCAD.2006.888291

DO - 10.1109/TCAD.2006.888291

M3 - Article

AN - SCOPUS:33847701654

SN - 0278-0070

VL - 26

SP - 447

EP - 454

JO - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

IS - 3

ER -

Low-power optimization by smart bit-width allocation in a systemC-based ASIC design environment

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Keywords

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