Low-power optimization by smart bit-width allocation in a systemC-based ASIC design environment

Arindam Mallik*, Debjit Sinha, Prithviraj Banerjee, Hai Zhou

*Corresponding author for this work

Research output: Contribution to journalArticle

24 Scopus citations

Abstract

The modern era of embedded system design is geared toward the design of low-power systems. One way to reduce power in an application-specified integrated circuit (ASIC) implementation is to reduce the bit-width precision of its computation units. This paper describes algorithms to optimize the bit widths of fixed-point variables for low power in a SystemC-based ASIC design environment. We propose an optimal bit-width allocation algorithm for two variables and a greedy heuristic that works for any number of variables. The algorithms are used in the automation of converting floating-point SystemC programs into ASIC synthesizable SystemC programs. Expected inputs are profiled to estimate errors in the finite precision conversions. Experimental results for the tradeoffs between quantization error, power consumption, and hardware resources used are reported on a set of four SystemC benchmarks that are mapped onto a 0.18-μm ASIC cell library from Artisan Components. We demonstrate that it is possible to reduce the power consumption by 50% on the average by allowing roundoff errors to increase from 0.5% to 1 %.

Original languageEnglish (US)
Pages (from-to)447-454
Number of pages8
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume26
Issue number3
DOIs
StatePublished - Mar 1 2007

Keywords

  • Fixed-point arithmetic
  • High-level synthesis
  • Low-power design
  • Quantization

ASJC Scopus subject areas

  • Software
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

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