Microarchitectures for managing chip revenues under process variations

Abhishek Das*, Serkan Ozdemir, Gokhan Memik, Joseph Zambreno, Alok Choudhary

*Corresponding author for this work

Research output: Contribution to journalArticle

6 Scopus citations

Abstract

As transistor feature sizes continue to shrink into the sub-90nm range and beyond, the effects of process variations on critical path delay and chip yields have amplified. A common concept to remedy the effects of variation is speed-binning, by which chips from a single batch are rated by a discrete range of frequencies and sold at different prices. In this paper, we discuss strategies to modify the number of chips in different bins and hence enhance the profits obtained from them. Particularly, we propose a scheme that introduces a small Substitute Cache associated with each cache way to replicate the data elements that will be stored in the high latency lines. Assuming a fixed pricing model, this method increases the revenue by as much as 13.8% without any impact on the performance of the chips.

Original languageEnglish (US)
Pages (from-to)29-32
Number of pages4
JournalIEEE Computer Architecture Letters
Volume6
Issue number2
DOIs
StatePublished - Feb 2007

Keywords

  • Cache memories
  • Computer architecture
  • Fault-tolerant computing
  • Process variations

ASJC Scopus subject areas

  • Hardware and Architecture

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