Minimal period retiming under process variations

Jia Wang; Hai Zhou

doi:10.1145/988952.988985

Minimal period retiming under process variations

Jia Wang^*, Hai Zhou

^*Corresponding author for this work

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Scopus citations

Abstract

With aggressive scaling down of feature sizes in VLSI fabrication, process variations have become a critical issue in designs. With process variations, timing optimization should consider the randomness introduced in delays. This paper considers how to retime a circuit under process variations. A statistical retiming problem is defined on the concept of a disutility function. Based on a new minimal period retiming algorithm, two algorithms are presented for the statistical retiming problem. Both theoretical and experimental results are given.

Original language	English (US)
Title of host publication	Proceedings of the 2004 ACM Great Lakes Symposium on VLSI, GLSVLSI 2004
Subtitle of host publication	VLSI in the Nanometer Era
Publisher	Association for Computing Machinery
Pages	131-135
Number of pages	5
ISBN (Print)	1581138539, 9781581138535
DOIs	https://doi.org/10.1145/988952.988985
State	Published - 2004
Event	Proceedings of the 2004 ACM Great lakes Symposium on VLSI, GLSVLSI 2004: VLSI in the Nanometer Era - Boston, MA, United States Duration: Apr 26 2004 → Apr 28 2004

Publication series

Name	Proceedings of the ACM Great Lakes Symposium on VLSI

Other

Other	Proceedings of the 2004 ACM Great lakes Symposium on VLSI, GLSVLSI 2004: VLSI in the Nanometer Era
Country/Territory	United States
City	Boston, MA
Period	4/26/04 → 4/28/04

Keywords

Process variations
Retiming
Statistical timing analysis

ASJC Scopus subject areas

General Engineering

Access to Document

10.1145/988952.988985

Cite this

@inproceedings{8b85a405b74e41109194c83d37c8607b,

title = "Minimal period retiming under process variations",

abstract = "With aggressive scaling down of feature sizes in VLSI fabrication, process variations have become a critical issue in designs. With process variations, timing optimization should consider the randomness introduced in delays. This paper considers how to retime a circuit under process variations. A statistical retiming problem is defined on the concept of a disutility function. Based on a new minimal period retiming algorithm, two algorithms are presented for the statistical retiming problem. Both theoretical and experimental results are given.",

keywords = "Process variations, Retiming, Statistical timing analysis",

author = "Jia Wang and Hai Zhou",

year = "2004",

doi = "10.1145/988952.988985",

language = "English (US)",

isbn = "1581138539",

series = "Proceedings of the ACM Great Lakes Symposium on VLSI",

publisher = "Association for Computing Machinery",

pages = "131--135",

booktitle = "Proceedings of the 2004 ACM Great Lakes Symposium on VLSI, GLSVLSI 2004",

note = "Proceedings of the 2004 ACM Great lakes Symposium on VLSI, GLSVLSI 2004: VLSI in the Nanometer Era ; Conference date: 26-04-2004 Through 28-04-2004",

}

Wang, J & Zhou, H 2004, Minimal period retiming under process variations. in Proceedings of the 2004 ACM Great Lakes Symposium on VLSI, GLSVLSI 2004: VLSI in the Nanometer Era. Proceedings of the ACM Great Lakes Symposium on VLSI, Association for Computing Machinery, pp. 131-135, Proceedings of the 2004 ACM Great lakes Symposium on VLSI, GLSVLSI 2004: VLSI in the Nanometer Era, Boston, MA, United States, 4/26/04. https://doi.org/10.1145/988952.988985

Minimal period retiming under process variations. / Wang, Jia; Zhou, Hai.
Proceedings of the 2004 ACM Great Lakes Symposium on VLSI, GLSVLSI 2004: VLSI in the Nanometer Era. Association for Computing Machinery, 2004. p. 131-135 (Proceedings of the ACM Great Lakes Symposium on VLSI).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Minimal period retiming under process variations

AU - Wang, Jia

AU - Zhou, Hai

PY - 2004

Y1 - 2004

N2 - With aggressive scaling down of feature sizes in VLSI fabrication, process variations have become a critical issue in designs. With process variations, timing optimization should consider the randomness introduced in delays. This paper considers how to retime a circuit under process variations. A statistical retiming problem is defined on the concept of a disutility function. Based on a new minimal period retiming algorithm, two algorithms are presented for the statistical retiming problem. Both theoretical and experimental results are given.

AB - With aggressive scaling down of feature sizes in VLSI fabrication, process variations have become a critical issue in designs. With process variations, timing optimization should consider the randomness introduced in delays. This paper considers how to retime a circuit under process variations. A statistical retiming problem is defined on the concept of a disutility function. Based on a new minimal period retiming algorithm, two algorithms are presented for the statistical retiming problem. Both theoretical and experimental results are given.

KW - Process variations

KW - Retiming

KW - Statistical timing analysis

UR - http://www.scopus.com/inward/record.url?scp=2942685030&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=2942685030&partnerID=8YFLogxK

U2 - 10.1145/988952.988985

DO - 10.1145/988952.988985

M3 - Conference contribution

AN - SCOPUS:2942685030

SN - 1581138539

SN - 9781581138535

T3 - Proceedings of the ACM Great Lakes Symposium on VLSI

SP - 131

EP - 135

BT - Proceedings of the 2004 ACM Great Lakes Symposium on VLSI, GLSVLSI 2004

PB - Association for Computing Machinery

T2 - Proceedings of the 2004 ACM Great lakes Symposium on VLSI, GLSVLSI 2004: VLSI in the Nanometer Era

Y2 - 26 April 2004 through 28 April 2004

ER -

Minimal period retiming under process variations

Abstract

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Other

Keywords

ASJC Scopus subject areas

Access to Document

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