Minimal period retiming under process variations

Jia Wang*, Hai Zhou

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

With aggressive scaling down of feature sizes in VLSI fabrication, process variations have become a critical issue in designs. With process variations, timing optimization should consider the randomness introduced in delays. This paper considers how to retime a circuit under process variations. A statistical retiming problem is defined on the concept of a disutility function. Based on a new minimal period retiming algorithm, two algorithms are presented for the statistical retiming problem. Both theoretical and experimental results are given.

Original languageEnglish (US)
Title of host publicationProceedings of the 2004 ACM Great Lakes Symposium on VLSI, GLSVLSI 2004
Subtitle of host publicationVLSI in the Nanometer Era
PublisherAssociation for Computing Machinery
Pages131-135
Number of pages5
ISBN (Print)1581138539, 9781581138535
DOIs
StatePublished - 2004
EventProceedings of the 2004 ACM Great lakes Symposium on VLSI, GLSVLSI 2004: VLSI in the Nanometer Era - Boston, MA, United States
Duration: Apr 26 2004Apr 28 2004

Publication series

NameProceedings of the ACM Great Lakes Symposium on VLSI

Other

OtherProceedings of the 2004 ACM Great lakes Symposium on VLSI, GLSVLSI 2004: VLSI in the Nanometer Era
CountryUnited States
CityBoston, MA
Period4/26/044/28/04

Keywords

  • Process variations
  • Retiming
  • Statistical timing analysis

ASJC Scopus subject areas

  • Engineering(all)

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  • Cite this

    Wang, J., & Zhou, H. (2004). Minimal period retiming under process variations. In Proceedings of the 2004 ACM Great Lakes Symposium on VLSI, GLSVLSI 2004: VLSI in the Nanometer Era (pp. 131-135). (Proceedings of the ACM Great Lakes Symposium on VLSI). Association for Computing Machinery. https://doi.org/10.1145/988952.988985