Modeling and analysis of leakage induced damping effect in low voltage LSIs

Gu Jie*, John Keane, Chris Kim

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

Although there has been extensive research on controlling leakage power, the fact that leaky transistors can act as a damping element for supply noise has been long ignored or unnoticed in the design community. This paper investigates the leakage induced damping effect that helps suppress the supply noise. By developing physics-based impedance models for active and leakage currents, we show that leakage, particularly gate tunneling leakage, provides more damping than strong-inversion current. Simulations were performed in a 32nm CMOS technology to validate our models under PVT variations and to explore the voltage dependent behavior of this phenomenon. Design example utilizing leakage induced damping such as decap assignment is discussed with results showing 15.6% saving in decap area.

Original languageEnglish (US)
Title of host publicationISLPED'06 - Proceedings of the 2006 International Symposium on Low Power Electronics and Design
Pages382-387
Number of pages6
Volume2006
DOIs
StatePublished - Dec 1 2006
EventISLPED'06 - 11th ACM/IEEE International Symposium on Low Power Electronics and Design - Tegernsee, Bavaria, Germany
Duration: Oct 4 2006Oct 6 2006

Other

OtherISLPED'06 - 11th ACM/IEEE International Symposium on Low Power Electronics and Design
CountryGermany
CityTegernsee, Bavaria
Period10/4/0610/6/06

Keywords

  • Damping effect
  • Gate leakage
  • Subthreshold leakage
  • Supply noise

ASJC Scopus subject areas

  • Engineering(all)

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    Jie, G., Keane, J., & Kim, C. (2006). Modeling and analysis of leakage induced damping effect in low voltage LSIs. In ISLPED'06 - Proceedings of the 2006 International Symposium on Low Power Electronics and Design (Vol. 2006, pp. 382-387) https://doi.org/10.1145/1165573.1165668