TY - GEN
T1 - Modeling and characterizing power variability in multicore architectures
AU - Meng, Ke
AU - Huebbers, Frank
AU - Joseph, Russell E
AU - Ismail, Yehea
PY - 2007
Y1 - 2007
N2 - Parameter variation due to manufacturing error will be an unavoidable consequence of technology scaling in future generations. The impact of random variation in physical factors such as gate length and interconnect spacing will have a profound impact on not only performance of chips, but also their power behavior. While circuit-level techniques such as adaptive body-biasing can help to mitigate mal-fabricated chips, they cannot completely alleviate severe within die variations forecasted for near future designs. Despite the large impact that power variability will have on future designs, there is a lack of published work that examines architectural implications of this phenomenon. In this work, we develop architecture level models that model power variability due to manufacturing error and examine its influence on multicore designs. We introduce VariPower, a tool for modeling power variability based on an microarchitectural description and floorplan of a chip. In particular, our models are based on layout level SPICE simulations and project power variability for different microarchitectural blocks using statistical analysis. Using VariPower, (1) we characterize power variability for multicore processors, (2) explore application sensitivity to power variability, and (3) examine clustering techniques that can appropriately classify groups of processors and chips that have similar variability characteristics.
AB - Parameter variation due to manufacturing error will be an unavoidable consequence of technology scaling in future generations. The impact of random variation in physical factors such as gate length and interconnect spacing will have a profound impact on not only performance of chips, but also their power behavior. While circuit-level techniques such as adaptive body-biasing can help to mitigate mal-fabricated chips, they cannot completely alleviate severe within die variations forecasted for near future designs. Despite the large impact that power variability will have on future designs, there is a lack of published work that examines architectural implications of this phenomenon. In this work, we develop architecture level models that model power variability due to manufacturing error and examine its influence on multicore designs. We introduce VariPower, a tool for modeling power variability based on an microarchitectural description and floorplan of a chip. In particular, our models are based on layout level SPICE simulations and project power variability for different microarchitectural blocks using statistical analysis. Using VariPower, (1) we characterize power variability for multicore processors, (2) explore application sensitivity to power variability, and (3) examine clustering techniques that can appropriately classify groups of processors and chips that have similar variability characteristics.
UR - http://www.scopus.com/inward/record.url?scp=34548334902&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=34548334902&partnerID=8YFLogxK
U2 - 10.1109/ISPASS.2007.363745
DO - 10.1109/ISPASS.2007.363745
M3 - Conference contribution
AN - SCOPUS:34548334902
SN - 1424410819
SN - 9781424410811
T3 - ISPASS 2007: IEEE International Symposium on Performance Analysis of Systems and Software
SP - 146
EP - 157
BT - ISPASS 2007
T2 - ISPASS 2007: IEEE International Symposium on Performance Analysis of Systems and Software
Y2 - 25 April 2007 through 27 April 2007
ER -