TY - JOUR
T1 - Monolithically Integrated Receiver Front End
T2 - In0.53Ga0.47As 53Ga, 47asp-i-n Amplifier
AU - Chang, Chu Liang Cheng
AU - Chang, R. P H
AU - Tell, Benjamin
AU - Zima Parker, Sandra M.
AU - Ota, Y.
AU - Vella-Coleiro, G. P.
AU - Miller, R. C.
AU - Zilko, John L.
AU - Kasper, B. L.
AU - Brown-Goebeler, Kevin F.
AU - Mattera, V. D.
PY - 1988/9
Y1 - 1988/9
N2 - Monolithically integrated InGaAs p-i-n-amplifiers have been successfully fabricated. The novel structure utilizes a vertical integration of a p-i-n diode and recessed-gate InP MISFET’s, while maintaining a planar surface for fine-line photolithography. The preamplifier consists of a gain stage and a buffer stage, both made of InP MISFET’s with aluminum phosphorus oxide as gate insulator. At 400 Mbit/s, the receiver sensitivity is better than -27 dBm for 1 x 10-9 bit error rate.
AB - Monolithically integrated InGaAs p-i-n-amplifiers have been successfully fabricated. The novel structure utilizes a vertical integration of a p-i-n diode and recessed-gate InP MISFET’s, while maintaining a planar surface for fine-line photolithography. The preamplifier consists of a gain stage and a buffer stage, both made of InP MISFET’s with aluminum phosphorus oxide as gate insulator. At 400 Mbit/s, the receiver sensitivity is better than -27 dBm for 1 x 10-9 bit error rate.
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U2 - 10.1109/16.2576
DO - 10.1109/16.2576
M3 - Article
AN - SCOPUS:0024070899
SN - 0018-9383
VL - 35
SP - 1439
EP - 1444
JO - IEEE Transactions on Electron Devices
JF - IEEE Transactions on Electron Devices
IS - 9
ER -