Multi-bit error tolerant caches using two-dimensional error coding

Jangwoo Kim*, Nikos Hardavellas, Ken Mai, Babak Falsafi, James C. Hoe

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

194 Scopus citations

Abstract

In deep sub-micron ICs, growing amounts of ondie memory and scaling effects make embedded memories increasingly vulnerable to reliability and yield problems. As scaling progresses, soft and hard errors in the memory system will increase and single error events are more likely to cause large-scale multi-bit errors. However, conventional memory protection techniques can neither detect nor correct large-scale multi-bit errors without incurring large performance, area, and power overheads. We propose two-dimensional (2D) error coding in embedded memories, a scalable multi-bit error protection technique to improve memory reliability and yield. The key innovation is the use of vertical error coding across words that is used only for error correction in combination with conventional per-word horizontal error coding. We evaluate this scheme in the cache hierarchies of two representative chip multiprocessor designs and show that 2D error coding can correct clustered errors up to 32x32 bits with significantly smaller performance, area, and power overheads than conventional techniques.

Original languageEnglish (US)
Title of host publicationProceedings of the The 40th IEEE/ACM International Symposium on Microarchitecture, MICRO 2007
Pages197-209
Number of pages13
DOIs
StatePublished - Dec 1 2007
Event40th IEEE/ACM International Symposium on Microarchitecture, MICRO 2007 - Chicago, IL, United States
Duration: Dec 1 2007Dec 5 2007

Publication series

NameProceedings of the Annual International Symposium on Microarchitecture, MICRO
ISSN (Print)1072-4451

Other

Other40th IEEE/ACM International Symposium on Microarchitecture, MICRO 2007
CountryUnited States
CityChicago, IL
Period12/1/0712/5/07

ASJC Scopus subject areas

  • Engineering(all)

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  • Cite this

    Kim, J., Hardavellas, N., Mai, K., Falsafi, B., & Hoe, J. C. (2007). Multi-bit error tolerant caches using two-dimensional error coding. In Proceedings of the The 40th IEEE/ACM International Symposium on Microarchitecture, MICRO 2007 (pp. 197-209). [4408256] (Proceedings of the Annual International Symposium on Microarchitecture, MICRO). https://doi.org/10.1109/MICRO.2007.19