TY - GEN
T1 - Multi-optimization power management for chip multiprocessors
AU - Meng, Ke
AU - Joseph, Russell E
AU - Dick, Robert P.
AU - Shang, Li
PY - 2008
Y1 - 2008
N2 - The emergence of power as a first-class design constraint has fueled the proposal of a growing number of run-time power optimizations. Many of these optimizations trade-off power saving opportunity for a variable performance loss which depends on application characteristics and program phase. Furthermore, the potential benefits of these optimizations are sometimes non-additive, and it can be difficult to identify which combinations of these optimizations to apply. Trial-and-error approaches have been proposed to adaptively tune a processor. However, in a chip multiprocessor, the cost of individually configuring each core under a wide range of optimizations would be prohibitive under simple trial-and-error approaches. In this work, we introduce an adaptive, multi-optimization power saving strategy for multi-core power management. Specifically, we solve the problem of meeting a global chip-wide power budget through run-time adaptation of highly configurable processor cores. Our approach applies analytic modeling to reduce exploration time and decrease the reliance on trial-and-error methods. We also introduce risk evaluation to balance the benefit of various power saving optimizations versus the potential performance loss. Overall, we find that our approach can significantly reduce processor power consumption compared to alternative optimization strategies.
AB - The emergence of power as a first-class design constraint has fueled the proposal of a growing number of run-time power optimizations. Many of these optimizations trade-off power saving opportunity for a variable performance loss which depends on application characteristics and program phase. Furthermore, the potential benefits of these optimizations are sometimes non-additive, and it can be difficult to identify which combinations of these optimizations to apply. Trial-and-error approaches have been proposed to adaptively tune a processor. However, in a chip multiprocessor, the cost of individually configuring each core under a wide range of optimizations would be prohibitive under simple trial-and-error approaches. In this work, we introduce an adaptive, multi-optimization power saving strategy for multi-core power management. Specifically, we solve the problem of meeting a global chip-wide power budget through run-time adaptation of highly configurable processor cores. Our approach applies analytic modeling to reduce exploration time and decrease the reliance on trial-and-error methods. We also introduce risk evaluation to balance the benefit of various power saving optimizations versus the potential performance loss. Overall, we find that our approach can significantly reduce processor power consumption compared to alternative optimization strategies.
KW - Cache Resizing
KW - Chip Multi-Processor
KW - Dynamic Power Management
KW - Voltage/Frequency Scaling
UR - http://www.scopus.com/inward/record.url?scp=63549102138&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=63549102138&partnerID=8YFLogxK
U2 - 10.1145/1454115.1454141
DO - 10.1145/1454115.1454141
M3 - Conference contribution
AN - SCOPUS:63549102138
SN - 9781605582825
T3 - Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT
SP - 177
EP - 186
BT - PACT'08
T2 - 17th International Conference on Parallel Architectures and Compilation Techniques, PACT 2008
Y2 - 25 October 2008 through 29 October 2008
ER -