Multi-Vdd design for content addressable memories (CAM): A power-delay optimization analysis

Siddhartha Joshi*, Dawei Li, Seda Ogrenci Memik, Grzegorz Deptuch, James Hoff, Sergo Jindariani, Tiehui Liu, Jamieson Olsen, Nhan Tran

*Corresponding author for this work

Research output: Contribution to journalArticle

5 Scopus citations

Abstract

In this paper, we characterize the interplay between power consumption and performance of a matchline-based Content Addressable Memory and then propose the use of a multi-Vdd design to save power and increase post-fabrication tunability. Exploration of the power consumption behavior of a CAM chip shows the drastically different behavior among the components and suggests the use of different and independent power supplies. The complete design, simulation and testing of a multi-Vdd CAM chip along with an exploration of the multi-Vdd design space are presented. Our analysis has been applied to simulated models on two different technology nodes (130 nm and 45 nm), followed by experiments on a 246-kb test chip fabricated in 130 nm Global Foundries Low Power CMOS technology. The proposed design, operating at an optimal operating point in a triple-Vdd configuration, increases the power-delay operation range by 2.4 times and consumes 25.3% less dynamic power when compared to a conventional single-Vdd design operating over the same voltage range with equivalent noise margin. Our multi-Vdd design also helps save 51.3% standby power. Measurement results from the test chip combined with the simulation analysis at the two nodes validate our thesis.

Original languageEnglish (US)
Article number25
JournalJournal of Low Power Electronics and Applications
Volume8
Issue number3
DOIs
StatePublished - Sep 2018

Keywords

  • Associative memory
  • Content addressable memory (CAM)
  • Matchline power
  • Multi supply
  • Multi-vdd
  • Searchline power
  • Standby power
  • TCAM
  • Tunable operation

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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