Multispeculative addition applied to datapath synthesis

Alberto A. Del Barrio*, Román Hermida, Seda Ogrenci Memik, José M. Mendias, María C. Molina

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

26 Scopus citations

Abstract

Addition is the key arithmetic operation in most digital circuits and processors. Therefore, their performance and other parameters, such as area and power consumption, are highly dependent on the adders' features. In this paper, we present multispeculation as a way of increasing adders' performance with a low area penalty. In our proposed design, dividing an adder into several fragments and predicting the carry-in of each fragment enables computing every addition in two very short cycles at the most, with 99% or higher probability. Furthermore, based on multispeculation principles, we propose a new strategy for implementing addition chains and hiding most of the penalty cycles due to mispredictions, while keeping at the same time the resource sharing capabilities that are sought in high-level synthesis. Our results show that it is possible to build linear and logarithmic adders more than 4.7× and 1.7 × faster than the nonspeculative case, respectively. Moreover, this is achieved with a low area penalty (38% for linear adders) or even an area reduction (-8% for logarithmic adders). Finally, applying multispeculation principles to signal processing benchmarks that use addition chains will result in 25% execution time reduction, with an additional 3% decrease in datapath area with respect to implementations with logarithmic fast adders.

Original languageEnglish (US)
Article number6349430
Pages (from-to)1817-1830
Number of pages14
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume31
Issue number12
DOIs
StatePublished - 2012

Funding

Manuscript received December 13, 2011; revised February 26, 2012 and May 21, 2012; accepted July 4, 2012. Date of current version November 21, 2012. This work was supported in part by the Spanish Government Research, under Grant TIN 2008/00508, and by the National Science Foundation, under Grant CNS-0546305. This paper was recommended by Associate Editor L. Pozzi.

Keywords

  • Adders design
  • datapath synthesis
  • speculation
  • variable latency

ASJC Scopus subject areas

  • Software
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

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