Near-optimal cache block placement with reactive nonuniform cache architectures

Nikos Hardavellas; Michael Ferdman; Babak Falsafi; Anastasia Ailamaki

doi:10.1109/MM.2010.22

Near-optimal cache block placement with reactive nonuniform cache architectures

Nikos Hardavellas^*, Michael Ferdman, Babak Falsafi, Anastasia Ailamaki

^*Corresponding author for this work

Computer Science

Research output: Contribution to journal › Article › peer-review

10 Scopus citations

Abstract

The growing core counts and caches of modern processors result in data access latency becoming a function of the data's physical location in the cache. Thus, the placement of cache blocks determines the cache's performance. Reactive nonuniform cache architectures (R-NUCA) achieve near-optimal cache block placement by classifying blocks online and placing data close to the cores that use them.

Original language	English (US)
Article number	5430736
Pages (from-to)	20-28
Number of pages	9
Journal	IEEE Micro
Volume	30
Issue number	1
DOIs	https://doi.org/10.1109/MM.2010.22
State	Published - Jan 2010

Funding

We would like to thank B. Gold, S. Somogyi and S. Herbert for their technical assistance, and T. Brecht, T. Strigkos, and the anonymous reviewers for their feedback. This work was partially supported by equipment donations from Intel; a Sloan research fellowship; a European Science Foundation European Young Investigator Award; and US National Science Foundation grants CCF-0702658, CCR-0509356, CCF-0845157,

Keywords

Cache memories
Data placement
Multicore
Nonuniform cache architectures
Parallel architectures

ASJC Scopus subject areas

Software
Hardware and Architecture
Electrical and Electronic Engineering

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10.1109/MM.2010.22

Cite this

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Near-optimal cache block placement with reactive nonuniform cache architectures

Abstract

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Keywords

ASJC Scopus subject areas

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