Near-optimal cache block placement with reactive nonuniform cache architectures

Nikos Hardavellas*, Michael Ferdman, Babak Falsafi, Anastasia Ailamaki

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

10 Scopus citations


The growing core counts and caches of modern processors result in data access latency becoming a function of the data's physical location in the cache. Thus, the placement of cache blocks determines the cache's performance. Reactive nonuniform cache architectures (R-NUCA) achieve near-optimal cache block placement by classifying blocks online and placing data close to the cores that use them.

Original languageEnglish (US)
Article number5430736
Pages (from-to)20-28
Number of pages9
JournalIEEE Micro
Issue number1
StatePublished - Jan 2010


  • Cache memories
  • Data placement
  • Multicore
  • Nonuniform cache architectures
  • Parallel architectures

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering


Dive into the research topics of 'Near-optimal cache block placement with reactive nonuniform cache architectures'. Together they form a unique fingerprint.

Cite this