The growing core counts and caches of modern processors result in data access latency becoming a function of the data's physical location in the cache. Thus, the placement of cache blocks determines the cache's performance. Reactive nonuniform cache architectures (R-NUCA) achieve near-optimal cache block placement by classifying blocks online and placing data close to the cores that use them.
- Cache memories
- Data placement
- Nonuniform cache architectures
- Parallel architectures
ASJC Scopus subject areas
- Hardware and Architecture
- Electrical and Electronic Engineering