Near-optimal cache block placement with reactive nonuniform cache architectures

Nikos Hardavellas; Michael Ferdman; Babak Falsafi; Anastasia Ailamaki

doi:10.1109/MM.2010.22

Near-optimal cache block placement with reactive nonuniform cache architectures

Nikos Hardavellas^*, Michael Ferdman, Babak Falsafi, Anastasia Ailamaki

^*Corresponding author for this work

Computer Science

Research output: Contribution to journal › Article › peer-review

9 Scopus citations

Abstract

The growing core counts and caches of modern processors result in data access latency becoming a function of the data's physical location in the cache. Thus, the placement of cache blocks determines the cache's performance. Reactive nonuniform cache architectures (R-NUCA) achieve near-optimal cache block placement by classifying blocks online and placing data close to the cores that use them.

Original language	English (US)
Article number	5430736
Pages (from-to)	20-28
Number of pages	9
Journal	IEEE Micro
Volume	30
Issue number	1
DOIs	https://doi.org/10.1109/MM.2010.22
State	Published - Jan 2010

Keywords

Cache memories
Data placement
Multicore
Nonuniform cache architectures
Parallel architectures

ASJC Scopus subject areas

Software
Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/MM.2010.22

Cite this

@article{1559e19132a241c1bc908f5293ea69d0,

title = "Near-optimal cache block placement with reactive nonuniform cache architectures",

abstract = "The growing core counts and caches of modern processors result in data access latency becoming a function of the data's physical location in the cache. Thus, the placement of cache blocks determines the cache's performance. Reactive nonuniform cache architectures (R-NUCA) achieve near-optimal cache block placement by classifying blocks online and placing data close to the cores that use them.",

keywords = "Cache memories, Data placement, Multicore, Nonuniform cache architectures, Parallel architectures",

author = "Nikos Hardavellas and Michael Ferdman and Babak Falsafi and Anastasia Ailamaki",

note = "Funding Information: We would like to thank B. Gold, S. Somogyi and S. Herbert for their technical assistance, and T. Brecht, T. Strigkos, and the anonymous reviewers for their feedback. This work was partially supported by equipment donations from Intel; a Sloan research fellowship; a European Science Foundation European Young Investigator Award; and US National Science Foundation grants CCF-0702658, CCR-0509356, CCF-0845157, Copyright: Copyright 2010 Elsevier B.V., All rights reserved.",

year = "2010",

month = jan,

doi = "10.1109/MM.2010.22",

language = "English (US)",

volume = "30",

pages = "20--28",

journal = "IEEE Micro",

issn = "0272-1732",

publisher = "IEEE Computer Society",

number = "1",

}

TY - JOUR

T1 - Near-optimal cache block placement with reactive nonuniform cache architectures

AU - Hardavellas, Nikos

AU - Ferdman, Michael

AU - Falsafi, Babak

AU - Ailamaki, Anastasia

N1 - Funding Information: We would like to thank B. Gold, S. Somogyi and S. Herbert for their technical assistance, and T. Brecht, T. Strigkos, and the anonymous reviewers for their feedback. This work was partially supported by equipment donations from Intel; a Sloan research fellowship; a European Science Foundation European Young Investigator Award; and US National Science Foundation grants CCF-0702658, CCR-0509356, CCF-0845157, Copyright: Copyright 2010 Elsevier B.V., All rights reserved.

PY - 2010/1

Y1 - 2010/1

N2 - The growing core counts and caches of modern processors result in data access latency becoming a function of the data's physical location in the cache. Thus, the placement of cache blocks determines the cache's performance. Reactive nonuniform cache architectures (R-NUCA) achieve near-optimal cache block placement by classifying blocks online and placing data close to the cores that use them.

AB - The growing core counts and caches of modern processors result in data access latency becoming a function of the data's physical location in the cache. Thus, the placement of cache blocks determines the cache's performance. Reactive nonuniform cache architectures (R-NUCA) achieve near-optimal cache block placement by classifying blocks online and placing data close to the cores that use them.

KW - Cache memories

KW - Data placement

KW - Multicore

KW - Nonuniform cache architectures

KW - Parallel architectures

UR - http://www.scopus.com/inward/record.url?scp=77949638926&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=77949638926&partnerID=8YFLogxK

U2 - 10.1109/MM.2010.22

DO - 10.1109/MM.2010.22

M3 - Article

AN - SCOPUS:77949638926

VL - 30

SP - 20

EP - 28

JO - IEEE Micro

JF - IEEE Micro

SN - 0272-1732

IS - 1

M1 - 5430736

ER -

Near-optimal cache block placement with reactive nonuniform cache architectures

Abstract

Keywords

ASJC Scopus subject areas

Access to Document

Other files and links

Cite this