Non-linear operating point statistical analysis for local variations in logic timing at low voltage

Rahul Rithe; Jie Gu; Alice Wang; Satyendra Datla; Gordon Gammie; Dennis Buss; Anantha Chandrakasan

doi:10.1109/date.2010.5456911

Non-linear operating point statistical analysis for local variations in logic timing at low voltage

Rahul Rithe^*, Jie Gu, Alice Wang, Satyendra Datla, Gordon Gammie, Dennis Buss, Anantha Chandrakasan

^*Corresponding author for this work

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

17 Scopus citations

Abstract

For CMOS feature size of 65 nm and below, local (or intra-die or within-die) variations in transistor Vt contribute stochastic variation in logic delay that is a large percentage of the nominal delay. Moreover, when circuits are operated at low voltage (Vdd ≤ 0.5V), the standard deviation of gate delay becomes comparable to nominal delay, and the Probability Density Function (PDF) of the gate delay is highly non-Gaussian. This paper presents a computationally efficient algorithm for computing the PDF of logic Timing Path (TP) delay, which results from local variations. This approach is called Non-linear Operating Point Analysis for Local Variations (NLOPALV). The approach is implemented using commercial STA tools and integrated into the standard CAD flow using custom scripts. Timing paths from a 28nm commercial DSP are analyzed using the proposed technique and the performance is observed to be within 5% accuracy compared to SPICE based Monte-Carlo analysis.

Original language	English (US)
Title of host publication	DATE 10 - Design, Automation and Test in Europe
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	965-968
Number of pages	4
ISBN (Print)	9783981080162
DOIs	https://doi.org/10.1109/date.2010.5456911
State	Published - 2010
Event	Design, Automation and Test in Europe Conference and Exhibition, DATE 2010 - Dresden, Germany Duration: Mar 8 2010 → Mar 12 2010

Publication series

Name	Proceedings -Design, Automation and Test in Europe, DATE
ISSN (Print)	1530-1591

Other

Other	Design, Automation and Test in Europe Conference and Exhibition, DATE 2010
Country/Territory	Germany
City	Dresden
Period	3/8/10 → 3/12/10

Keywords

Local variations
Low-voltage
SSTA
Statistical design

ASJC Scopus subject areas

General Engineering

Access to Document

10.1109/date.2010.5456911

Cite this

Rithe, R., Gu, J., Wang, A., Datla, S., Gammie, G., Buss, D., & Chandrakasan, A. (2010). Non-linear operating point statistical analysis for local variations in logic timing at low voltage. In DATE 10 - Design, Automation and Test in Europe (pp. 965-968). Article 5456911 (Proceedings -Design, Automation and Test in Europe, DATE). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/date.2010.5456911

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title = "Non-linear operating point statistical analysis for local variations in logic timing at low voltage",

abstract = "For CMOS feature size of 65 nm and below, local (or intra-die or within-die) variations in transistor Vt contribute stochastic variation in logic delay that is a large percentage of the nominal delay. Moreover, when circuits are operated at low voltage (Vdd ≤ 0.5V), the standard deviation of gate delay becomes comparable to nominal delay, and the Probability Density Function (PDF) of the gate delay is highly non-Gaussian. This paper presents a computationally efficient algorithm for computing the PDF of logic Timing Path (TP) delay, which results from local variations. This approach is called Non-linear Operating Point Analysis for Local Variations (NLOPALV). The approach is implemented using commercial STA tools and integrated into the standard CAD flow using custom scripts. Timing paths from a 28nm commercial DSP are analyzed using the proposed technique and the performance is observed to be within 5\% accuracy compared to SPICE based Monte-Carlo analysis.",

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Rithe, R, Gu, J, Wang, A, Datla, S, Gammie, G, Buss, D & Chandrakasan, A 2010, Non-linear operating point statistical analysis for local variations in logic timing at low voltage. in DATE 10 - Design, Automation and Test in Europe., 5456911, Proceedings -Design, Automation and Test in Europe, DATE, Institute of Electrical and Electronics Engineers Inc., pp. 965-968, Design, Automation and Test in Europe Conference and Exhibition, DATE 2010, Dresden, Germany, 3/8/10. https://doi.org/10.1109/date.2010.5456911

Non-linear operating point statistical analysis for local variations in logic timing at low voltage. / Rithe, Rahul; Gu, Jie; Wang, Alice et al.
DATE 10 - Design, Automation and Test in Europe. Institute of Electrical and Electronics Engineers Inc., 2010. p. 965-968 5456911 (Proceedings -Design, Automation and Test in Europe, DATE).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AU - Rithe, Rahul

AU - Gu, Jie

AU - Wang, Alice

AU - Datla, Satyendra

AU - Gammie, Gordon

AU - Buss, Dennis

AU - Chandrakasan, Anantha

PY - 2010

Y1 - 2010

N2 - For CMOS feature size of 65 nm and below, local (or intra-die or within-die) variations in transistor Vt contribute stochastic variation in logic delay that is a large percentage of the nominal delay. Moreover, when circuits are operated at low voltage (Vdd ≤ 0.5V), the standard deviation of gate delay becomes comparable to nominal delay, and the Probability Density Function (PDF) of the gate delay is highly non-Gaussian. This paper presents a computationally efficient algorithm for computing the PDF of logic Timing Path (TP) delay, which results from local variations. This approach is called Non-linear Operating Point Analysis for Local Variations (NLOPALV). The approach is implemented using commercial STA tools and integrated into the standard CAD flow using custom scripts. Timing paths from a 28nm commercial DSP are analyzed using the proposed technique and the performance is observed to be within 5% accuracy compared to SPICE based Monte-Carlo analysis.

AB - For CMOS feature size of 65 nm and below, local (or intra-die or within-die) variations in transistor Vt contribute stochastic variation in logic delay that is a large percentage of the nominal delay. Moreover, when circuits are operated at low voltage (Vdd ≤ 0.5V), the standard deviation of gate delay becomes comparable to nominal delay, and the Probability Density Function (PDF) of the gate delay is highly non-Gaussian. This paper presents a computationally efficient algorithm for computing the PDF of logic Timing Path (TP) delay, which results from local variations. This approach is called Non-linear Operating Point Analysis for Local Variations (NLOPALV). The approach is implemented using commercial STA tools and integrated into the standard CAD flow using custom scripts. Timing paths from a 28nm commercial DSP are analyzed using the proposed technique and the performance is observed to be within 5% accuracy compared to SPICE based Monte-Carlo analysis.

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Rithe R, Gu J, Wang A, Datla S, Gammie G, Buss D et al. Non-linear operating point statistical analysis for local variations in logic timing at low voltage. In DATE 10 - Design, Automation and Test in Europe. Institute of Electrical and Electronics Engineers Inc. 2010. p. 965-968. 5456911. (Proceedings -Design, Automation and Test in Europe, DATE). doi: 10.1109/date.2010.5456911

Non-linear operating point statistical analysis for local variations in logic timing at low voltage

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