@inproceedings{70759e45a7554fcc831c00f94125bad7,
title = "Non-linear operating point statistical analysis for local variations in logic timing at low voltage",
abstract = "For CMOS feature size of 65 nm and below, local (or intra-die or within-die) variations in transistor Vt contribute stochastic variation in logic delay that is a large percentage of the nominal delay. Moreover, when circuits are operated at low voltage (Vdd ≤ 0.5V), the standard deviation of gate delay becomes comparable to nominal delay, and the Probability Density Function (PDF) of the gate delay is highly non-Gaussian. This paper presents a computationally efficient algorithm for computing the PDF of logic Timing Path (TP) delay, which results from local variations. This approach is called Non-linear Operating Point Analysis for Local Variations (NLOPALV). The approach is implemented using commercial STA tools and integrated into the standard CAD flow using custom scripts. Timing paths from a 28nm commercial DSP are analyzed using the proposed technique and the performance is observed to be within 5% accuracy compared to SPICE based Monte-Carlo analysis.",
keywords = "Local variations, Low-voltage, SSTA, Statistical design",
author = "Rahul Rithe and Jie Gu and Alice Wang and Satyendra Datla and Gordon Gammie and Dennis Buss and Anantha Chandrakasan",
note = "Copyright: Copyright 2020 Elsevier B.V., All rights reserved.; Design, Automation and Test in Europe Conference and Exhibition, DATE 2010 ; Conference date: 08-03-2010 Through 12-03-2010",
year = "2010",
doi = "10.1109/date.2010.5456911",
language = "English (US)",
isbn = "9783981080162",
series = "Proceedings -Design, Automation and Test in Europe, DATE",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "965--968",
booktitle = "DATE 10 - Design, Automation and Test in Europe",
address = "United States",
}