TY - GEN
T1 - Numerical investigation of channel width variation in junctionless transistors performance
AU - Dehzangi, Arash
AU - Larki, Farhad
AU - Majlis, Burhanuddin Y.
AU - Hamidon, M. N.
AU - Menon, P. Susthitha
AU - Jalar, Azman
AU - Islam, Md Shabiul
AU - Ali, Sawal Hamid Md
PY - 2013/12/1
Y1 - 2013/12/1
N2 - Double gate junctionless (DGJLT) transistor, as a pinch off device, was previously fabricated. In this letter, the impact of channel width variation on behaviour of the device is studied by means of 3D-TCAD simulation tool. In this matter, the transfer characteristics, energy band diagram (valence/conduction band) and normal electric field along the nanowire between the source and the drain are studied at pinch off state. By decreasing the nanowire width, the on current decreases. Threshold voltage also reduced by decreasing the wire width. The highest electric field occurs at off state and the normal component of the electric field is stronger for smaller channel width. At pinch off state, the energy band diagrams revealed that a potential barrier against the current flow was built in channel which the smallest width has higher potential barrier. The overall result agrees with the behaviour of the nanowire junctionless transistors.
AB - Double gate junctionless (DGJLT) transistor, as a pinch off device, was previously fabricated. In this letter, the impact of channel width variation on behaviour of the device is studied by means of 3D-TCAD simulation tool. In this matter, the transfer characteristics, energy band diagram (valence/conduction band) and normal electric field along the nanowire between the source and the drain are studied at pinch off state. By decreasing the nanowire width, the on current decreases. Threshold voltage also reduced by decreasing the wire width. The highest electric field occurs at off state and the normal component of the electric field is stronger for smaller channel width. At pinch off state, the energy band diagrams revealed that a potential barrier against the current flow was built in channel which the smallest width has higher potential barrier. The overall result agrees with the behaviour of the nanowire junctionless transistors.
KW - Lateral gate Junctionless transistor
KW - TCAD simulation
KW - channel width effect
KW - energy band diagram
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U2 - 10.1109/RSM.2013.6706483
DO - 10.1109/RSM.2013.6706483
M3 - Conference contribution
AN - SCOPUS:84893620020
SN - 9781479911837
T3 - Proceedings - RSM 2013: 2013 IEEE Regional Symposium on Micro and Nano Electronics
SP - 101
EP - 104
BT - Proceedings - RSM 2013
T2 - 2013 IEEE Regional Symposium on Micro and Nano Electronics, RSM 2013
Y2 - 25 September 2013 through 27 September 2013
ER -