Numerical study of side gate junction-less transistor in on state

Arash Dehzangi, Farhad Larki, Burhanuddin Y. Majlis, M. N. Hamidon, Manizheh Navasery, Elham Gharibshahi, Nasrin Khalilzadeh, Mohammadmahdi Vakilian, Elias B. Saion

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Side gate p-type Junctionless Silicon transistor is fabricated by AFM nanolithography on low-doped (105 cm-3) SOI wafer. In this work, the simulation characteristic of the device using TCAD Sentaurus in on state will be studied. The results show that the device is the pinch off transistor, works in on state for zero gate voltage in depletion mode. Negative gate voltage drives the device into on state, but unable to make significant effect on drain current as accmulation mode. Simulation results for valence band energy, electric field and hole density are investigated along the active regions. The influence of the electric field due to the applied voltages of VDS and VG on charge distribution is much more when the device operates at the saturation region. The hole quasi-Fermi level has a positive slope showing the current flows from source to drain.

Original languageEnglish (US)
Title of host publicationProceedings - RSM 2013
Subtitle of host publication2013 IEEE Regional Symposium on Micro and Nano Electronics
Pages398-401
Number of pages4
DOIs
StatePublished - Dec 1 2013
Event2013 IEEE Regional Symposium on Micro and Nano Electronics, RSM 2013 - Langkawi, Malaysia
Duration: Sep 25 2013Sep 27 2013

Publication series

NameProceedings - RSM 2013: 2013 IEEE Regional Symposium on Micro and Nano Electronics

Other

Other2013 IEEE Regional Symposium on Micro and Nano Electronics, RSM 2013
CountryMalaysia
CityLangkawi
Period9/25/139/27/13

Keywords

  • Side gate Junctionless Transistors (SGJLT)
  • hole density distribution
  • valence band energy

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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