Abstract
With the rapid evolution of the IC supply chain, circuit IP protection has become a critical realistic issue for the semiconductor industry. One promising technique to resolve the issue is logic locking. It adds key inputs to the original circuit such that only authorized users can get the correct function, and it modifies the circuit to obfuscate it against structural analysis. However, there is a trilemma among locking, obfuscation, and efficiency within all existing logic locking methods that at most two of the objectives can be achieved. In this work, we propose ObfusLock, the first logic locking method that simultaneously achieves all three objectives: locking security, obfuscation safety, and locking efficiency. ObfusLock is based on solid mathematical proofs, incurs small overheads (<5% on average), and has passed experimental tests of various existing attacks.
Original language | English (US) |
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Title of host publication | 2023 Design, Automation and Test in Europe Conference and Exhibition, DATE 2023 - Proceedings |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
ISBN (Electronic) | 9783981926378 |
DOIs | |
State | Published - 2023 |
Event | 2023 Design, Automation and Test in Europe Conference and Exhibition, DATE 2023 - Antwerp, Belgium Duration: Apr 17 2023 → Apr 19 2023 |
Publication series
Name | Proceedings -Design, Automation and Test in Europe, DATE |
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Volume | 2023-April |
ISSN (Print) | 1530-1591 |
Conference
Conference | 2023 Design, Automation and Test in Europe Conference and Exhibition, DATE 2023 |
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Country/Territory | Belgium |
City | Antwerp |
Period | 4/17/23 → 4/19/23 |
Funding
by the National Science Foundation
Keywords
- IP piracy
- SAT attack
- hardware obfuscation
- logic locking
- logic synthesis
ASJC Scopus subject areas
- General Engineering