Optimal gate sizing for coupling-noise reduction

Debjit Sinha, Hai Zhou, Chris C.N. Chu

Research output: Contribution to conferencePaper

5 Scopus citations

Abstract

Coupling-noise reduction has emerged as a critical design problem with VLSI feature sizes shrinking rapidly and with the use of more aggressive and less noise-immune circuits. Since coupling-noise on a net depends on driving gate-sizes of the net itself and all nets coupled to it, gate-sizing emerges as an effective approach to coupling-noise reduction. It is an attractive approach since re-routing is not required. In this paper, we propose an iterative gate-sizing algorithm to determine optimal gate-sizes for coupling-noise reduction. We consider gate-sizing as a fixpoint computation on a complete lattice and the beauty of the iterative gate-sizing algorithm lies in its ability to guarantee the optimal solution, provided it exists. The effectiveness of the algorithm is validated experimentally by simulations on multiple large circuits.

Original languageEnglish (US)
Pages176-181
Number of pages6
StatePublished - Jun 28 2004
EventProceedings of the International Symposium on Physical Design, ISPD 2004 - Phoenix, AZ, United States
Duration: Apr 18 2004Apr 21 2004

Other

OtherProceedings of the International Symposium on Physical Design, ISPD 2004
CountryUnited States
CityPhoenix, AZ
Period4/18/044/21/04

Keywords

  • Coupling-Noise
  • Fixpoint
  • Gate-Sizing
  • Lattice Theory

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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    Sinha, D., Zhou, H., & Chu, C. C. N. (2004). Optimal gate sizing for coupling-noise reduction. 176-181. Paper presented at Proceedings of the International Symposium on Physical Design, ISPD 2004, Phoenix, AZ, United States.