Optimizing wirelength and routability by searching alternative packings in floorplanning

Chiu Wing Sham*, Evangeline F.Y. Young, Hai Zhou

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

1 Scopus citations


Recent advances in VLSI technology have made optimization of the interconnect delay and routability of a circuit more important. We should consider interconnect planning as early as possible. We propose a postfloorplanning step to reduce the interconnect cost of a floorplan by searching alternative packings. If a packing contains a rectangular bounding box of a group of modules, we can rearrange the blocks in the bounding box to obtain a new floorplan with the same area, but possibly with a smaller interconnect cost. Experimental results show that we can reduce the interconnect cost of a packing without any penalty in area.

Original languageEnglish (US)
Article number21
JournalACM Transactions on Design Automation of Electronic Systems
Issue number1
StatePublished - Jan 1 2008


  • Floorplanning
  • Wirelength reduction

ASJC Scopus subject areas

  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering


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