Overview of a Compiler for Synthesizing MATLAB Programs onto FPGAs

Prithviraj Banerjee*, Malay Haldar, Anshuman Nayak, Victor Kim, Vikram Saxena, Steven Parkes, Debabrata Bagchi, Satrajit Pal, Nikhil Tripathi, David Zaretsky, Robert Anderson, Juan Ramon Uribe

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

16 Scopus citations


This paper describes a behavioral synthesis tool called AccelFPGA which reads in high-level descriptions of digital signal processing (DSP) applications written in MATLAB, and automatically generates synthesizable register transfer level (RTL) models and simulation testbenches in VHDL or Verilog. The RTL models can be synthesized using commercial logic synthesis tools and place and route tools onto field-programmable gate arrays (FPGAs). This paper describes how powerful directives are used to provide high-level architectural tradeoffs for the DSP designer. Experimental results are reported on a set of eight MATLAB benchmarks that are mapped onto the Xilinx Virtex II and Altera Stratix FPGAs.

Original languageEnglish (US)
Pages (from-to)312-324
Number of pages13
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Issue number3
StatePublished - Mar 2004


  • Field-programmable gate arrays (FPGAs)
  • High-level synthesis
  • Register transfer level (RTL)
  • Verilog
  • VHDL

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering


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