Overview of a Compiler for Synthesizing MATLAB Programs onto FPGAs

Prithviraj Banerjee; Malay Haldar; Anshuman Nayak; Victor Kim; Vikram Saxena; Steven Parkes; Debabrata Bagchi; Satrajit Pal; Nikhil Tripathi; David Zaretsky; Robert Anderson; Juan Ramon Uribe

doi:10.1109/TVLSI.2004.824301

Overview of a Compiler for Synthesizing MATLAB Programs onto FPGAs

Prithviraj Banerjee^*, Malay Haldar, Anshuman Nayak, Victor Kim, Vikram Saxena, Steven Parkes, Debabrata Bagchi, Satrajit Pal, Nikhil Tripathi, David Zaretsky, Robert Anderson, Juan Ramon Uribe

^*Corresponding author for this work

Electrical and Computer Engineering

Research output: Contribution to journal › Article › peer-review

16 Scopus citations

Abstract

This paper describes a behavioral synthesis tool called AccelFPGA which reads in high-level descriptions of digital signal processing (DSP) applications written in MATLAB, and automatically generates synthesizable register transfer level (RTL) models and simulation testbenches in VHDL or Verilog. The RTL models can be synthesized using commercial logic synthesis tools and place and route tools onto field-programmable gate arrays (FPGAs). This paper describes how powerful directives are used to provide high-level architectural tradeoffs for the DSP designer. Experimental results are reported on a set of eight MATLAB benchmarks that are mapped onto the Xilinx Virtex II and Altera Stratix FPGAs.

Original language	English (US)
Pages (from-to)	312-324
Number of pages	13
Journal	IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume	12
Issue number	3
DOIs	https://doi.org/10.1109/TVLSI.2004.824301
State	Published - Mar 2004

Keywords

Field-programmable gate arrays (FPGAs)
High-level synthesis
MATLAB
Register transfer level (RTL)
Verilog
VHDL

ASJC Scopus subject areas

Software
Hardware and Architecture
Electrical and Electronic Engineering

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10.1109/TVLSI.2004.824301

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abstract = "This paper describes a behavioral synthesis tool called AccelFPGA which reads in high-level descriptions of digital signal processing (DSP) applications written in MATLAB, and automatically generates synthesizable register transfer level (RTL) models and simulation testbenches in VHDL or Verilog. The RTL models can be synthesized using commercial logic synthesis tools and place and route tools onto field-programmable gate arrays (FPGAs). This paper describes how powerful directives are used to provide high-level architectural tradeoffs for the DSP designer. Experimental results are reported on a set of eight MATLAB benchmarks that are mapped onto the Xilinx Virtex II and Altera Stratix FPGAs.",

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AU - Saxena, Vikram

AU - Parkes, Steven

AU - Bagchi, Debabrata

AU - Pal, Satrajit

AU - Tripathi, Nikhil

AU - Zaretsky, David

AU - Anderson, Robert

AU - Uribe, Juan Ramon

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Overview of a Compiler for Synthesizing MATLAB Programs onto FPGAs

Abstract

Keywords

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