Package design challenges and optimizations in density efficient (Intel® Xeon® processor D) SoC

Qi Zhu, Srikrishnan Venkataraman, Chunfei Ye, Arun Chandrasekhar

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

Xeon®-D[1] brings the high performance of Xeon® processors into a dense, low-power System-on-Chip (SoC). This paper addresses the importance of cost-performance trade off optimization for the Xeon®-D package. It describes how to determine the low cost package factors (size, footprint, pin map and layer count) without compromising the performance of the system. 10GbE signal integrity design and HSD pin map optimization are discussed. Low power architecture and package power delivery features including FIVR are presented in the paper as well.

Original languageEnglish (US)
Title of host publication2016 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages47-49
Number of pages3
ISBN (Electronic)9781509061846
DOIs
StatePublished - Apr 5 2017
Event2016 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2016 - Honolulu, United States
Duration: Dec 14 2016Dec 16 2016

Other

Other2016 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2016
CountryUnited States
CityHonolulu
Period12/14/1612/16/16

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials
  • Modeling and Simulation

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