Package design challenges and optimizations in density efficient (Intel® Xeon® processor D) SoC

Qi Zhu; Srikrishnan Venkataraman; Chunfei Ye; Arun Chandrasekhar

doi:10.1109/EDAPS.2016.7893122

Package design challenges and optimizations in density efficient (Intel® Xeon® processor D) SoC

Qi Zhu, Srikrishnan Venkataraman, Chunfei Ye, Arun Chandrasekhar

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Scopus citations

Abstract

Xeon®-D[1] brings the high performance of Xeon® processors into a dense, low-power System-on-Chip (SoC). This paper addresses the importance of cost-performance trade off optimization for the Xeon®-D package. It describes how to determine the low cost package factors (size, footprint, pin map and layer count) without compromising the performance of the system. 10GbE signal integrity design and HSD pin map optimization are discussed. Low power architecture and package power delivery features including FIVR are presented in the paper as well.

Original language	English (US)
Title of host publication	2016 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2016
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	47-49
Number of pages	3
ISBN (Electronic)	9781509061846
DOIs	https://doi.org/10.1109/EDAPS.2016.7893122
State	Published - Apr 5 2017
Event	2016 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2016 - Honolulu, United States Duration: Dec 14 2016 → Dec 16 2016

Other

Other	2016 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2016
Country/Territory	United States
City	Honolulu
Period	12/14/16 → 12/16/16

ASJC Scopus subject areas

Electrical and Electronic Engineering
Electronic, Optical and Magnetic Materials
Modeling and Simulation

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10.1109/EDAPS.2016.7893122

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Zhu, Q., Venkataraman, S., Ye, C., & Chandrasekhar, A. (2017). Package design challenges and optimizations in density efficient (Intel® Xeon® processor D) SoC. In 2016 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2016 (pp. 47-49). Article 7893122 Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/EDAPS.2016.7893122

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title = "Package design challenges and optimizations in density efficient (Intel{\textregistered} Xeon{\textregistered} processor D) SoC",

abstract = "Xeon{\textregistered}-D[1] brings the high performance of Xeon{\textregistered} processors into a dense, low-power System-on-Chip (SoC). This paper addresses the importance of cost-performance trade off optimization for the Xeon{\textregistered}-D package. It describes how to determine the low cost package factors (size, footprint, pin map and layer count) without compromising the performance of the system. 10GbE signal integrity design and HSD pin map optimization are discussed. Low power architecture and package power delivery features including FIVR are presented in the paper as well.",

author = "Qi Zhu and Srikrishnan Venkataraman and Chunfei Ye and Arun Chandrasekhar",

year = "2017",

month = apr,

day = "5",

doi = "10.1109/EDAPS.2016.7893122",

language = "English (US)",

pages = "47--49",

booktitle = "2016 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2016",

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note = "2016 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2016 ; Conference date: 14-12-2016 Through 16-12-2016",

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Zhu, Q, Venkataraman, S, Ye, C & Chandrasekhar, A 2017, Package design challenges and optimizations in density efficient (Intel® Xeon® processor D) SoC. in 2016 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2016., 7893122, Institute of Electrical and Electronics Engineers Inc., pp. 47-49, 2016 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2016, Honolulu, United States, 12/14/16. https://doi.org/10.1109/EDAPS.2016.7893122

Package design challenges and optimizations in density efficient (Intel® Xeon® processor D) SoC. / Zhu, Qi; Venkataraman, Srikrishnan; Ye, Chunfei et al.
2016 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2016. Institute of Electrical and Electronics Engineers Inc., 2017. p. 47-49 7893122.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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N2 - Xeon®-D[1] brings the high performance of Xeon® processors into a dense, low-power System-on-Chip (SoC). This paper addresses the importance of cost-performance trade off optimization for the Xeon®-D package. It describes how to determine the low cost package factors (size, footprint, pin map and layer count) without compromising the performance of the system. 10GbE signal integrity design and HSD pin map optimization are discussed. Low power architecture and package power delivery features including FIVR are presented in the paper as well.

AB - Xeon®-D[1] brings the high performance of Xeon® processors into a dense, low-power System-on-Chip (SoC). This paper addresses the importance of cost-performance trade off optimization for the Xeon®-D package. It describes how to determine the low cost package factors (size, footprint, pin map and layer count) without compromising the performance of the system. 10GbE signal integrity design and HSD pin map optimization are discussed. Low power architecture and package power delivery features including FIVR are presented in the paper as well.

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M3 - Conference contribution

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BT - 2016 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2016

PB - Institute of Electrical and Electronics Engineers Inc.

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Package design challenges and optimizations in density efficient (Intel® Xeon® processor D) SoC

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