Package Design Optimization for Intel SoC Xeon-D

Qi Zhu; Srikrishnan Venkataraman; Chunfei Ye; Arun Chandrasekhar; Cesar Mendez Ruiz

doi:10.1109/TCPMT.2017.2783259

Package Design Optimization for Intel SoC Xeon-D

Qi Zhu, Srikrishnan Venkataraman, Chunfei Ye, Arun Chandrasekhar, Cesar Mendez Ruiz

Electrical and Computer Engineering

Research output: Contribution to journal › Article › peer-review

5 Scopus citations

Abstract

Xeon-D brings the high performance of Xeon processors into a dense, low-power system-on-chip. This paper addresses the importance of cost-performance tradeoff analysis for the Xeon-D package. It describes how to determine the low-cost package factors (size, footprint, pin map, and layer count) without compromising the performance of the system. The 10-GbE signal integrity design and high-speed differential cost-performance optimization are discussed. Low-power architecture and package power delivery features including fully integrated voltage regulator are presented in this paper as well.

Original language	English (US)
Pages (from-to)	531-537
Number of pages	7
Journal	IEEE Transactions on Components, Packaging and Manufacturing Technology
Volume	8
Issue number	4
DOIs	https://doi.org/10.1109/TCPMT.2017.2783259
State	Published - Apr 2018

Keywords

Ball grid array (BGA)
optimization
package
pinmap
system-on-chip

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Industrial and Manufacturing Engineering
Electrical and Electronic Engineering

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10.1109/TCPMT.2017.2783259

Cite this

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title = "Package Design Optimization for Intel SoC Xeon-D",

abstract = "Xeon-D brings the high performance of Xeon processors into a dense, low-power system-on-chip. This paper addresses the importance of cost-performance tradeoff analysis for the Xeon-D package. It describes how to determine the low-cost package factors (size, footprint, pin map, and layer count) without compromising the performance of the system. The 10-GbE signal integrity design and high-speed differential cost-performance optimization are discussed. Low-power architecture and package power delivery features including fully integrated voltage regulator are presented in this paper as well.",

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author = "Qi Zhu and Srikrishnan Venkataraman and Chunfei Ye and Arun Chandrasekhar and Ruiz, {Cesar Mendez}",

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AB - Xeon-D brings the high performance of Xeon processors into a dense, low-power system-on-chip. This paper addresses the importance of cost-performance tradeoff analysis for the Xeon-D package. It describes how to determine the low-cost package factors (size, footprint, pin map, and layer count) without compromising the performance of the system. The 10-GbE signal integrity design and high-speed differential cost-performance optimization are discussed. Low-power architecture and package power delivery features including fully integrated voltage regulator are presented in this paper as well.

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KW - pinmap

KW - system-on-chip

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Package Design Optimization for Intel SoC Xeon-D

Abstract

Keywords

ASJC Scopus subject areas

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