Package Design Optimization for Intel SoC Xeon-D

Qi Zhu, Srikrishnan Venkataraman, Chunfei Ye, Arun Chandrasekhar, Cesar Mendez Ruiz

Research output: Contribution to journalArticlepeer-review

5 Scopus citations


Xeon-D brings the high performance of Xeon processors into a dense, low-power system-on-chip. This paper addresses the importance of cost-performance tradeoff analysis for the Xeon-D package. It describes how to determine the low-cost package factors (size, footprint, pin map, and layer count) without compromising the performance of the system. The 10-GbE signal integrity design and high-speed differential cost-performance optimization are discussed. Low-power architecture and package power delivery features including fully integrated voltage regulator are presented in this paper as well.

Original languageEnglish (US)
Pages (from-to)531-537
Number of pages7
JournalIEEE Transactions on Components, Packaging and Manufacturing Technology
Issue number4
StatePublished - Apr 2018


  • Ball grid array (BGA)
  • optimization
  • package
  • pinmap
  • system-on-chip

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Industrial and Manufacturing Engineering
  • Electrical and Electronic Engineering


Dive into the research topics of 'Package Design Optimization for Intel SoC Xeon-D'. Together they form a unique fingerprint.

Cite this