Parallel algorithms for FPGA placement

Malay Haldar*, Anshuman Nayak, Alok Nidhi Choudhary, Prith Banerjee

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

21 Scopus citations

Abstract

Fast FPGA CAD tools that produce high quality results has been one of the most important research issues in the FPGA domain. Simulated annealing has been the method of choice for placement. However, simulated annealing is a very compute-intensive method. In our present work we investigate a range of parallelization strategies to speedup simulated annealing with application to placement for FPGA. We present experimental results obtained by applying the different parallelization strategies to the Versatile Place and Route (VPR) Tool, implemented on an SGI Origin shared memory multiprocessor and an IBM-SP2 distributed memory multiprocessor. The results show the tradeoff between execution time and quality of result for the different parallelization strategies.

Original languageEnglish (US)
Pages (from-to)86-94
Number of pages9
JournalProceedings of the IEEE Great Lakes Symposium on VLSI
StatePublished - Jan 1 2000
EventGLSVLSI 2000: 10th Great Lakes Symposium on VLSI - Chicago, IL, USA
Duration: Mar 2 2000Mar 4 2000

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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