Parallel algorithms for FPGA placement

Malay Haldar; Anshuman Nayak; Alok Choudhary; Prith Banerjee

doi:10.1145/330855.330988

Parallel algorithms for FPGA placement

Malay Haldar^*, Anshuman Nayak, Alok Choudhary, Prith Banerjee

^*Corresponding author for this work

Electrical and Computer Engineering

Research output: Contribution to journal › Conference article › peer-review

24 Scopus citations

Abstract

Fast FPGA CAD tools that produce high quality results has been one of the most important research issues in the FPGA domain. Simulated annealing has been the method of choice for placement. However, simulated annealing is a very compute-intensive method. In our present work we investigate a range of parallelization strategies to speedup simulated annealing with application to placement for FPGA. We present experimental results obtained by applying the different parallelization strategies to the Versatile Place and Route (VPR) Tool, implemented on an SGI Origin shared memory multiprocessor and an IBM-SP2 distributed memory multiprocessor. The results show the tradeoff between execution time and quality of result for the different parallelization strategies.

Original language	English (US)
Pages (from-to)	86-94
Number of pages	9
Journal	Proceedings of the IEEE Great Lakes Symposium on VLSI
DOIs	https://doi.org/10.1145/330855.330988
State	Published - 2000
Event	GLSVLSI 2000: 10th Great Lakes Symposium on VLSI - Chicago, IL, USA Duration: Mar 2 2000 → Mar 4 2000

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1145/330855.330988

Cite this

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abstract = "Fast FPGA CAD tools that produce high quality results has been one of the most important research issues in the FPGA domain. Simulated annealing has been the method of choice for placement. However, simulated annealing is a very compute-intensive method. In our present work we investigate a range of parallelization strategies to speedup simulated annealing with application to placement for FPGA. We present experimental results obtained by applying the different parallelization strategies to the Versatile Place and Route (VPR) Tool, implemented on an SGI Origin shared memory multiprocessor and an IBM-SP2 distributed memory multiprocessor. The results show the tradeoff between execution time and quality of result for the different parallelization strategies.",

author = "Malay Haldar and Anshuman Nayak and Alok Choudhary and Prith Banerjee",

year = "2000",

doi = "10.1145/330855.330988",

language = "English (US)",

pages = "86--94",

journal = "Proceedings of the IEEE Great Lakes Symposium on VLSI",

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T1 - Parallel algorithms for FPGA placement

AU - Haldar, Malay

AU - Nayak, Anshuman

AU - Choudhary, Alok

AU - Banerjee, Prith

PY - 2000

Y1 - 2000

N2 - Fast FPGA CAD tools that produce high quality results has been one of the most important research issues in the FPGA domain. Simulated annealing has been the method of choice for placement. However, simulated annealing is a very compute-intensive method. In our present work we investigate a range of parallelization strategies to speedup simulated annealing with application to placement for FPGA. We present experimental results obtained by applying the different parallelization strategies to the Versatile Place and Route (VPR) Tool, implemented on an SGI Origin shared memory multiprocessor and an IBM-SP2 distributed memory multiprocessor. The results show the tradeoff between execution time and quality of result for the different parallelization strategies.

AB - Fast FPGA CAD tools that produce high quality results has been one of the most important research issues in the FPGA domain. Simulated annealing has been the method of choice for placement. However, simulated annealing is a very compute-intensive method. In our present work we investigate a range of parallelization strategies to speedup simulated annealing with application to placement for FPGA. We present experimental results obtained by applying the different parallelization strategies to the Versatile Place and Route (VPR) Tool, implemented on an SGI Origin shared memory multiprocessor and an IBM-SP2 distributed memory multiprocessor. The results show the tradeoff between execution time and quality of result for the different parallelization strategies.

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Parallel algorithms for FPGA placement

Abstract

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