Paths to fast barrier synchronization on the node

Conor Hetland, Georgios Tziantzioulis, Brian Suchy, Michael Leonard, Jin Han, John Albers, Nikos Hardavellas, Peter Dinda

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

Synchronization primitives like barriers heavily impact the performance of parallel programs. As core counts increase and granularity decreases, the value of enabling fast barriers increases. Through the evaluation of the performance of a variety of software implementations of barriers, we found the cost of software barriers to be on the order of tens of thousands of cycles on various incarnations of x64 hardware. We argue that reducing the latency of a barrier via hardware support will dramatically improve the performance of existing applications and runtimes, and would enable new execution models, including those which currently do not perform well on multicore machines. To support our argument, we first present the design, implementation, and evaluation of a barrier on the Intel HARP, a prototype that integrates an x64 processor and FPGA in the same package. This effort gives insight into the potential speed and compactness of hardware barriers, and suggests useful improvements to the HARP platform. Next, we turn to the processor itself and describe an x64 ISA extension for barriers, and how it could be implemented in the microarchitecture with minimal collateral changes. This design allows for barriers to be securely managed jointly between the OS and the application. Finally, we speculate on how barrier synchronization might be implemented on future photonics-based hardware.

Original languageEnglish (US)
Title of host publicationHPDC 2019- Proceedings of the 28th International Symposium on High-Performance Parallel and Distributed Computing
PublisherAssociation for Computing Machinery, Inc
Pages109-120
Number of pages12
ISBN (Electronic)9781450366700
DOIs
StatePublished - Jun 17 2019
Event28th ACM International Symposium on High-Performance Parallel and Distributed Computing, HPDC 2019 - Phoenix, United States
Duration: Jun 22 2019Jun 29 2019

Publication series

NameHPDC 2019- Proceedings of the 28th International Symposium on High-Performance Parallel and Distributed Computing

Conference

Conference28th ACM International Symposium on High-Performance Parallel and Distributed Computing, HPDC 2019
Country/TerritoryUnited States
CityPhoenix
Period6/22/196/29/19

Keywords

  • Collective communication
  • HPC
  • Parallel computing
  • Synchronization

ASJC Scopus subject areas

  • Computational Theory and Mathematics
  • Computer Science Applications
  • Software

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