Performance implications of transient loop-carried data dependences in automatically parallelized loops

Niall Murphy, Timothy Jones, Robert Mullins, Simone Campanoni

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Scopus citations

Abstract

Recent approaches to automatic parallelization have taken advantage of the low-latency on-chip interconnect provided in modern multicore processors, demonstrating significant speedups, even for complex workloads. Although these techniques can already extract significant thread-level parallelism from application loops, we are interested in quantifying and exploiting any additional performance that remains on the table. This paper confirms the existence of significant extra threadlevel parallelism within loops parallelized by the HELIX compiler. However, improving static data dependence analysis is unable to reach the additional performance offered because the existing loopcarried dependences are true only on a small subset of loop iterations. We therefore develop three approaches to take advantage of the transient nature of these data dependences through speculation, via transactional memory support. Results show that coupling the state-of-the-art data dependence analysis with fine-grained speculation achieves most of the speedups and may help close the gap towards the limit of HELIX-style thread-level parallelism.

Original languageEnglish (US)
Title of host publicationProceedings of CC 2016
Subtitle of host publicationThe 25th International Conference on Compiler Construction
PublisherAssociation for Computing Machinery, Inc
Pages23-33
Number of pages11
ISBN (Electronic)9781450342414
DOIs
StatePublished - Mar 17 2016
Event25th International Conference on Compiler Construction, CC 2016 - Barcelona, Spain
Duration: Mar 17 2016Mar 18 2016

Publication series

NameProceedings of CC 2016: The 25th International Conference on Compiler Construction

Other

Other25th International Conference on Compiler Construction, CC 2016
CountrySpain
CityBarcelona
Period3/17/163/18/16

Keywords

  • Thread-level speculation
  • Transactional memory

ASJC Scopus subject areas

  • Hardware and Architecture
  • Signal Processing
  • Software

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