Pessimism reduction in coupling-aware static timing analysis using timing and logic filtering

Debasish Das*, Kip Killpack, Chandramouli Kashyap, Abhijit Jas, Hai Zhou

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

Abstract

With continued scaling of technology into nanometer regimes, the impact of coupling induced delay variations is significant. While several coupling-aware static timers have been proposed, the results are often pessimistic with many false failures. We present an integrated iterative timing filtering and logic filtering based approach to reduce pessimism. We use a realistic coupling model based on arrival times and slews, and show that non-iterative pessimism reduction algorithms proposed in previous research may give potentially non-conservative timing results. On a functional block from an industrial 65 nm microprocessor, our algorithm produced a maximum pessimism reduction of 11.18% of cycle time over converged timing filtering analysis that does not consider logic constraints.

Original languageEnglish (US)
Article number5419240
Pages (from-to)466-478
Number of pages13
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume29
Issue number3
DOIs
StatePublished - Mar 1 2010

Keywords

  • Interconnect
  • Physical design
  • SAT
  • Signal integrity
  • Timing analysis
  • Timing verification

ASJC Scopus subject areas

  • Software
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

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