Pinch-off mechanism in double-lateral-gate junctionless transistors fabricated by scanning probe microscope based lithography

Farhad Larki*, Arash Dehzangi, Alam Abedini, Ahmad Makarimi Abdullah, Elias Saion, Sabar D. Hutagalung, Mohd N. Hamidon, Jumiah Hassan

*Corresponding author for this work

Research output: Contribution to journalArticle

11 Scopus citations

Abstract

A double-lateral-gate p-type junctionless transistor is fabricated on a low-doped (1015) silicon-on-insulator wafer by a lithography technique based on scanning probe microscopy and two steps of wet chemical etching. The experimental transfer characteristics are obtained and compared with the numerical characteristics of the device. The simulation results are used to investigate the pinch-off mechanism, from the flat band to the off state. The study is based on the variation of the carrier density and the electric-field components. The device is a pinch-off transistor, which is normally in the on state and is driven into the off state by the application of a positive gate voltage. We demonstrate that the depletion starts from the bottom corner of the channel facing the gates and expands toward the center and top of the channel. Redistribution of the carriers due to the electric field emanating from the gates creates an electric field perpendicular to the current, toward the bottom of the channel, which provides the electrostatic squeezing of the current.

Original languageEnglish (US)
Pages (from-to)817-823
Number of pages7
JournalBeilstein Journal of Nanotechnology
Volume3
Issue number1
DOIs
StatePublished - 2012

Keywords

  • AFM nanolithography
  • Junctionless transistors
  • Pinch-off
  • Scanning probe microscope
  • Simulation © 2012 Larki et al.

ASJC Scopus subject areas

  • Materials Science(all)
  • Physics and Astronomy(all)
  • Electrical and Electronic Engineering

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