Power-driven design partitioning

Rajarshi Mukherjee, Seda Ogrenci Memik

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

In order to enable efficient integration of FPGAs into cost effective and reliable high-performance systems as well potentially into low power mobile systems, their power efficiency needs to be improved. In this paper, we propose a power management scheme for FPGAs centered on a power-driven partitioning technique. Our power-driven partitioner creates clusters within a design such that within individual clusters, power consumption can be improved via voltage scaling. We tested the effectiveness of our approach on a set of LUT-level benchmark netlists. Further we did constrained placement of the clusters into predefined Vddhigh and Vddlow regions for a single FPGA. Average savings in power consumption with our approach is 48% whereas penalty in channel width and wire length due to constrained placement is 23% and 26% respectively.

Original languageEnglish (US)
Title of host publicationLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
EditorsJurgen Becker, Marco Platzner, Serge Vernalde
PublisherSpringer Verlag
Pages740-750
Number of pages11
ISBN (Print)3540229892, 9783540229896
DOIs
StatePublished - 2004
Event14th International Conference on Field Programmable Logic and Applications, FPL 2004 - Antwerp, Belgium
Duration: Aug 30 2004Sep 1 2004

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume3203
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349

Other

Other14th International Conference on Field Programmable Logic and Applications, FPL 2004
Country/TerritoryBelgium
CityAntwerp
Period8/30/049/1/04

ASJC Scopus subject areas

  • Theoretical Computer Science
  • Computer Science(all)

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