Power management for FPGAs: Power- driven design partitioning

Rajarshi Mukherjee, Seda Ogrenci Memik

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

A power management scheme for FPGAs centered on a power-driven partitioning technique was proposed. The partitioner creates clusters within a design such that within individual clusters, power consumption can be improved by voltage scaling. Algorithms aimed at performing power-driven partitioning were presented and two applications, such as chip-level power management for multi-FPGA systems, and single chip power optimization were formulated using localized voltage scaling. The study show that power improvements as high as 54% is achievable if the number of partitions is not restricted.

Original languageEnglish (US)
Title of host publicationProceedings - 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2004
EditorsJ. Arnold, K.L. Pocek
Pages326-327
Number of pages2
DOIs
StatePublished - Dec 1 2004
EventProceedings - 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2004 - Napa, CA, United States
Duration: Apr 20 2004Apr 23 2004

Publication series

NameProceedings - 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2004

Other

OtherProceedings - 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2004
CountryUnited States
CityNapa, CA
Period4/20/044/23/04

ASJC Scopus subject areas

  • Engineering(all)

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  • Cite this

    Mukherjee, R., & Memik, S. O. (2004). Power management for FPGAs: Power- driven design partitioning. In J. Arnold, & K. L. Pocek (Eds.), Proceedings - 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2004 (pp. 326-327). (Proceedings - 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2004). https://doi.org/10.1109/FCCM.2004.45