Pre-synthesis area estimation of reconfigurable streaming accelerators

Somsubhra Mondal*, Seda Ogrenci Memik, Nikolaos Bellas

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Scopus citations

Abstract

One of the major challenges in automated synthesis of reconfigurable accelerators is to create efficient designs that conform to the resource capacity of the target device. This work concerns estimation of the hardware cost before actually attempting the synthesis of streaming accelerators on reconfigurable platforms. Specifically, our proposed framework tackles the problem of pre-synthesis estimation of data queuing cost, while incorporating the potential impact of resource constraints on the final implementation. We present a probabilistic push-and-pull approach for register queue size estimation of a streaming data flow graph. We evaluated our techniques using an industrial toolflow. For the register queue sizes our estimations are within the range of-14.4% to 12.4% on an average, for various resource constraints on a set of multimedia applications.

Original languageEnglish (US)
Title of host publicationProceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL
Pages813-816
Number of pages4
DOIs
StatePublished - Dec 1 2006
Event2006 International Conference on Field Programmable Logic and Applications, FPL - Madrid, Spain
Duration: Aug 28 2006Aug 30 2006

Other

Other2006 International Conference on Field Programmable Logic and Applications, FPL
CountrySpain
CityMadrid
Period8/28/068/30/06

ASJC Scopus subject areas

  • Computational Theory and Mathematics
  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'Pre-synthesis area estimation of reconfigurable streaming accelerators'. Together they form a unique fingerprint.

  • Cite this

    Mondal, S., Memik, S. O., & Bellas, N. (2006). Pre-synthesis area estimation of reconfigurable streaming accelerators. In Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL (pp. 813-816). [4101082] https://doi.org/10.1109/FPL.2006.311320