Process variation aware cache leakage management

Ke Meng*, Russell E Joseph

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

52 Scopus citations

Abstract

In a few technology generations, limitations of fabrication processes will make accurate design time power estimates a daunting challenge. Static leakage current which comprises a significant fraction of total power due to large on-chip caches, is exponentially dependent on widely varying physical parameters such as gate length, gate oxide thickness, and dopant ion concentration. In large structures like on-chip caches, this may mean that one portion of a cache may consume an order of magnitude larger static power than equivalently sized regions. Under this climate, egalitarian management of physical resources is clearly untenable. In this paper, we analyze the effects of within-die and die-to-die leakage variation for on-chip caches. We then propose way prioritization, a manufacturing variation aware scheme that minimizes cache leakage energy. Our results show that significant average power reductions are possible without undue hardware complexity or performance compromise.

Original languageEnglish (US)
Title of host publicationISLPED'06 - Proceedings of the 2006 International Symposium on Low Power Electronics and Design
Pages262-267
Number of pages6
DOIs
StatePublished - 2006
EventISLPED'06 - 11th ACM/IEEE International Symposium on Low Power Electronics and Design - Tegernsee, Bavaria, Germany
Duration: Oct 4 2006Oct 6 2006

Publication series

NameProceedings of the International Symposium on Low Power Electronics and Design
Volume2006
ISSN (Print)1533-4678

Other

OtherISLPED'06 - 11th ACM/IEEE International Symposium on Low Power Electronics and Design
CountryGermany
CityTegernsee, Bavaria
Period10/4/0610/6/06

Keywords

  • Cache management
  • Gated-VDD
  • Leakage
  • Low power
  • Process variation
  • Selective cache ways

ASJC Scopus subject areas

  • Engineering(all)

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