Quantifying and coping with parametric variations in 3D-stacked microarchitectures

Serkan Ozdemir*, Yan Pan, Abhishek Das, Gokhan Memik, Gabriel Loh, Alok Nidhi Choudhary

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

16 Scopus citations


Variability in device characteristics, i.e., parametric variations, is an important problem for shrinking process technologies. They manifest themselves as variations in performance, power consumption, and reduction in reliability in the manufactured chips as well as low yield levels. Their implications on performance and yield are particularly profound on 3D architectures: a defect on even a single layer can render the entire stack useless. In this paper, we show that instead of causing increased yield losses, we can actually exploit 3D technology to reduce yield losses by intelligently devising the architectures. We take advantage of the layer-to-layer variations to reduce yield losses by splitting critical components among multiple layers. Our results indicate that our proposed method achieves a 30.6% lower yield loss rate compared to the same pipeline implemented on a 2D architecture.

Original languageEnglish (US)
Title of host publicationProceedings of the 47th Design Automation Conference, DAC '10
Number of pages6
StatePublished - 2010
Event47th Design Automation Conference, DAC '10 - Anaheim, CA, United States
Duration: Jun 13 2010Jun 18 2010

Publication series

NameProceedings - Design Automation Conference
ISSN (Print)0738-100X


Other47th Design Automation Conference, DAC '10
Country/TerritoryUnited States
CityAnaheim, CA


  • 3D Integration
  • Cache Architectures
  • Process Variations
  • Processor Pipeline

ASJC Scopus subject areas

  • Computer Science Applications
  • Control and Systems Engineering
  • Electrical and Electronic Engineering
  • Modeling and Simulation


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