TY - GEN
T1 - Quick reconfiguration in clustered micro-sequencer
AU - Jafari, Roozbeh
AU - Memik, Seda Ogrenci
AU - Sarrafzadeh, Majid
PY - 2005
Y1 - 2005
N2 - This paper presents a Micro-Sequencer based reconfigurable system. We introduce the concept of Quick Reconfiguration and compare it with existing "full reconfiguration " schemes. In a typical scenario, reconfiguring a system from one application to another does not require a "full" reconfiguration. Instead we can exploit similarities among various applications to save on reconfiguration time. We show that a significant speedup is gained, by using quick reconfiguration on a set of image processing benchmarks, which takes seconds versus hours in traditional FPGA reconfigurations. We evaluate the flexibility, the performance and the parallelism of this architecture with customized functional units. Furthermore, a method was proposed for customizing clustered datapath to improve the throughput of the system. This method accelerates the system by 13 times on average compared to the case where the same algorithm is running on a modern processor. We also map various applications directly onto FPGAs and measure the silicon area and the power consumption and compare to the case where the applications are implemented on micro-sequencers. On average, micro-sequencer takes 31% more area and consumes 23% more power. However, the reconfiguration time is decreased to less than one second on average while for applications directly mapped onto FPGAs, it is near 3000 seconds.
AB - This paper presents a Micro-Sequencer based reconfigurable system. We introduce the concept of Quick Reconfiguration and compare it with existing "full reconfiguration " schemes. In a typical scenario, reconfiguring a system from one application to another does not require a "full" reconfiguration. Instead we can exploit similarities among various applications to save on reconfiguration time. We show that a significant speedup is gained, by using quick reconfiguration on a set of image processing benchmarks, which takes seconds versus hours in traditional FPGA reconfigurations. We evaluate the flexibility, the performance and the parallelism of this architecture with customized functional units. Furthermore, a method was proposed for customizing clustered datapath to improve the throughput of the system. This method accelerates the system by 13 times on average compared to the case where the same algorithm is running on a modern processor. We also map various applications directly onto FPGAs and measure the silicon area and the power consumption and compare to the case where the applications are implemented on micro-sequencers. On average, micro-sequencer takes 31% more area and consumes 23% more power. However, the reconfiguration time is decreased to less than one second on average while for applications directly mapped onto FPGAs, it is near 3000 seconds.
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U2 - 10.1109/IPDPS.2005.370
DO - 10.1109/IPDPS.2005.370
M3 - Conference contribution
AN - SCOPUS:33746278164
SN - 0769523129
SN - 0769523129
SN - 9780769523125
T3 - Proceedings - 19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005
SP - 150b
BT - Proceedings - 19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005
T2 - 19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005
Y2 - 4 April 2005 through 8 April 2005
ER -