@inproceedings{cb6eb99d019e43c988583bef1e8cf38c,
title = "R-Accelerator: A Reconfigurable Accelerator with RRAM Based Logic Contraction and Resource Optimization for Application Specific Computing",
abstract = "In this paper, we introduce a novel reconfigurable accelerator (R-Accelerator) design which embeds RRAM device into traditional logic circuits for high-performance application specific computing. To facilitate the synthesis of the proposed RRAM based logic cell, a special logic contraction technique is developed to maximize the area saving. In order to optimize the arithmetic unit array for instruction set mapping and interconnect routing, a new resource allocation algorithm is also proposed to achieve further saving in area and power. Using a fully integrated design flow with commercial design tools, our experimental results show that the proposed RRAM based R-Accelerator architecture offers 45% area improvement, 33% power reduction and 32% performance enhancement in a 45nm CMOS process compared with conventional CMOS design.",
keywords = "RRAM, Reconfigurable architecture, logic contraction, memristor",
author = "Zhengyu Chen and Hai Zhou and Jie Gu",
note = "Funding Information: This work is funded by NSF grant CCF-1533656. Funding Information: NSF grant CCF-1533656.; 36th International Conference on Computer Design, ICCD 2018 ; Conference date: 07-10-2018 Through 10-10-2018",
year = "2019",
month = jan,
day = "16",
doi = "10.1109/ICCD.2018.00034",
language = "English (US)",
series = "Proceedings - 2018 IEEE 36th International Conference on Computer Design, ICCD 2018",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "163--170",
booktitle = "Proceedings - 2018 IEEE 36th International Conference on Computer Design, ICCD 2018",
address = "United States",
}