Abstract
In this paper, we introduce a novel reconfigurable accelerator (R-Accelerator) design which embeds RRAM device into traditional logic circuits for high-performance application specific computing. To facilitate the synthesis of the proposed RRAM based logic cell, a special logic contraction technique is developed to maximize the area saving. In order to optimize the arithmetic unit array for instruction set mapping and interconnect routing, a new resource allocation algorithm is also proposed to achieve further saving in area and power. Using a fully integrated design flow with commercial design tools, our experimental results show that the proposed RRAM based R-Accelerator architecture offers 45% area improvement, 33% power reduction and 32% performance enhancement in a 45nm CMOS process compared with conventional CMOS design.
| Original language | English (US) |
|---|---|
| Title of host publication | Proceedings - 2018 IEEE 36th International Conference on Computer Design, ICCD 2018 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 163-170 |
| Number of pages | 8 |
| ISBN (Electronic) | 9781538684771 |
| DOIs | |
| State | Published - Jan 16 2019 |
| Event | 36th International Conference on Computer Design, ICCD 2018 - Orlando, United States Duration: Oct 7 2018 → Oct 10 2018 |
Publication series
| Name | Proceedings - 2018 IEEE 36th International Conference on Computer Design, ICCD 2018 |
|---|
Conference
| Conference | 36th International Conference on Computer Design, ICCD 2018 |
|---|---|
| Country | United States |
| City | Orlando |
| Period | 10/7/18 → 10/10/18 |
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Keywords
- RRAM
- Reconfigurable architecture
- logic contraction
- memristor
ASJC Scopus subject areas
- Computer Networks and Communications
- Hardware and Architecture
- Safety, Risk, Reliability and Quality
Cite this
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R-Accelerator : A Reconfigurable Accelerator with RRAM Based Logic Contraction and Resource Optimization for Application Specific Computing. / Chen, Zhengyu; Zhou, Hai; Gu, Jie.
Proceedings - 2018 IEEE 36th International Conference on Computer Design, ICCD 2018. Institute of Electrical and Electronics Engineers Inc., 2019. p. 163-170 8615684 (Proceedings - 2018 IEEE 36th International Conference on Computer Design, ICCD 2018).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
TY - GEN
T1 - R-Accelerator
T2 - A Reconfigurable Accelerator with RRAM Based Logic Contraction and Resource Optimization for Application Specific Computing
AU - Chen, Zhengyu
AU - Zhou, Hai
AU - Gu, Jie
PY - 2019/1/16
Y1 - 2019/1/16
N2 - In this paper, we introduce a novel reconfigurable accelerator (R-Accelerator) design which embeds RRAM device into traditional logic circuits for high-performance application specific computing. To facilitate the synthesis of the proposed RRAM based logic cell, a special logic contraction technique is developed to maximize the area saving. In order to optimize the arithmetic unit array for instruction set mapping and interconnect routing, a new resource allocation algorithm is also proposed to achieve further saving in area and power. Using a fully integrated design flow with commercial design tools, our experimental results show that the proposed RRAM based R-Accelerator architecture offers 45% area improvement, 33% power reduction and 32% performance enhancement in a 45nm CMOS process compared with conventional CMOS design.
AB - In this paper, we introduce a novel reconfigurable accelerator (R-Accelerator) design which embeds RRAM device into traditional logic circuits for high-performance application specific computing. To facilitate the synthesis of the proposed RRAM based logic cell, a special logic contraction technique is developed to maximize the area saving. In order to optimize the arithmetic unit array for instruction set mapping and interconnect routing, a new resource allocation algorithm is also proposed to achieve further saving in area and power. Using a fully integrated design flow with commercial design tools, our experimental results show that the proposed RRAM based R-Accelerator architecture offers 45% area improvement, 33% power reduction and 32% performance enhancement in a 45nm CMOS process compared with conventional CMOS design.
KW - RRAM
KW - Reconfigurable architecture
KW - logic contraction
KW - memristor
UR - http://www.scopus.com/inward/record.url?scp=85062232805&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85062232805&partnerID=8YFLogxK
U2 - 10.1109/ICCD.2018.00034
DO - 10.1109/ICCD.2018.00034
M3 - Conference contribution
T3 - Proceedings - 2018 IEEE 36th International Conference on Computer Design, ICCD 2018
SP - 163
EP - 170
BT - Proceedings - 2018 IEEE 36th International Conference on Computer Design, ICCD 2018
PB - Institute of Electrical and Electronics Engineers Inc.
ER -