R-Accelerator: A Reconfigurable Accelerator with RRAM Based Logic Contraction and Resource Optimization for Application Specific Computing

Zhengyu Chen, Hai Zhou, Jie Gu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper, we introduce a novel reconfigurable accelerator (R-Accelerator) design which embeds RRAM device into traditional logic circuits for high-performance application specific computing. To facilitate the synthesis of the proposed RRAM based logic cell, a special logic contraction technique is developed to maximize the area saving. In order to optimize the arithmetic unit array for instruction set mapping and interconnect routing, a new resource allocation algorithm is also proposed to achieve further saving in area and power. Using a fully integrated design flow with commercial design tools, our experimental results show that the proposed RRAM based R-Accelerator architecture offers 45% area improvement, 33% power reduction and 32% performance enhancement in a 45nm CMOS process compared with conventional CMOS design.

Original languageEnglish (US)
Title of host publicationProceedings - 2018 IEEE 36th International Conference on Computer Design, ICCD 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages163-170
Number of pages8
ISBN (Electronic)9781538684771
DOIs
StatePublished - Jan 16 2019
Event36th International Conference on Computer Design, ICCD 2018 - Orlando, United States
Duration: Oct 7 2018Oct 10 2018

Publication series

NameProceedings - 2018 IEEE 36th International Conference on Computer Design, ICCD 2018

Conference

Conference36th International Conference on Computer Design, ICCD 2018
CountryUnited States
CityOrlando
Period10/7/1810/10/18

Fingerprint

Particle accelerators
Logic circuits
Resource allocation
RRAM

Keywords

  • RRAM
  • Reconfigurable architecture
  • logic contraction
  • memristor

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Hardware and Architecture
  • Safety, Risk, Reliability and Quality

Cite this

Chen, Z., Zhou, H., & Gu, J. (2019). R-Accelerator: A Reconfigurable Accelerator with RRAM Based Logic Contraction and Resource Optimization for Application Specific Computing. In Proceedings - 2018 IEEE 36th International Conference on Computer Design, ICCD 2018 (pp. 163-170). [8615684] (Proceedings - 2018 IEEE 36th International Conference on Computer Design, ICCD 2018). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICCD.2018.00034
Chen, Zhengyu ; Zhou, Hai ; Gu, Jie. / R-Accelerator : A Reconfigurable Accelerator with RRAM Based Logic Contraction and Resource Optimization for Application Specific Computing. Proceedings - 2018 IEEE 36th International Conference on Computer Design, ICCD 2018. Institute of Electrical and Electronics Engineers Inc., 2019. pp. 163-170 (Proceedings - 2018 IEEE 36th International Conference on Computer Design, ICCD 2018).
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abstract = "In this paper, we introduce a novel reconfigurable accelerator (R-Accelerator) design which embeds RRAM device into traditional logic circuits for high-performance application specific computing. To facilitate the synthesis of the proposed RRAM based logic cell, a special logic contraction technique is developed to maximize the area saving. In order to optimize the arithmetic unit array for instruction set mapping and interconnect routing, a new resource allocation algorithm is also proposed to achieve further saving in area and power. Using a fully integrated design flow with commercial design tools, our experimental results show that the proposed RRAM based R-Accelerator architecture offers 45{\%} area improvement, 33{\%} power reduction and 32{\%} performance enhancement in a 45nm CMOS process compared with conventional CMOS design.",
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Chen, Z, Zhou, H & Gu, J 2019, R-Accelerator: A Reconfigurable Accelerator with RRAM Based Logic Contraction and Resource Optimization for Application Specific Computing. in Proceedings - 2018 IEEE 36th International Conference on Computer Design, ICCD 2018., 8615684, Proceedings - 2018 IEEE 36th International Conference on Computer Design, ICCD 2018, Institute of Electrical and Electronics Engineers Inc., pp. 163-170, 36th International Conference on Computer Design, ICCD 2018, Orlando, United States, 10/7/18. https://doi.org/10.1109/ICCD.2018.00034

R-Accelerator : A Reconfigurable Accelerator with RRAM Based Logic Contraction and Resource Optimization for Application Specific Computing. / Chen, Zhengyu; Zhou, Hai; Gu, Jie.

Proceedings - 2018 IEEE 36th International Conference on Computer Design, ICCD 2018. Institute of Electrical and Electronics Engineers Inc., 2019. p. 163-170 8615684 (Proceedings - 2018 IEEE 36th International Conference on Computer Design, ICCD 2018).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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AB - In this paper, we introduce a novel reconfigurable accelerator (R-Accelerator) design which embeds RRAM device into traditional logic circuits for high-performance application specific computing. To facilitate the synthesis of the proposed RRAM based logic cell, a special logic contraction technique is developed to maximize the area saving. In order to optimize the arithmetic unit array for instruction set mapping and interconnect routing, a new resource allocation algorithm is also proposed to achieve further saving in area and power. Using a fully integrated design flow with commercial design tools, our experimental results show that the proposed RRAM based R-Accelerator architecture offers 45% area improvement, 33% power reduction and 32% performance enhancement in a 45nm CMOS process compared with conventional CMOS design.

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Chen Z, Zhou H, Gu J. R-Accelerator: A Reconfigurable Accelerator with RRAM Based Logic Contraction and Resource Optimization for Application Specific Computing. In Proceedings - 2018 IEEE 36th International Conference on Computer Design, ICCD 2018. Institute of Electrical and Electronics Engineers Inc. 2019. p. 163-170. 8615684. (Proceedings - 2018 IEEE 36th International Conference on Computer Design, ICCD 2018). https://doi.org/10.1109/ICCD.2018.00034