Abstract
In this paper, we investigate methods for improving the hit rates in the first level of memory hierarchy. Particularly, we propose victim cache structures to reduce the number of accesses to more power consuming structures such as level 2 caches. We compare the proposed victim cache techniques to increasing the associativity or the size of the level 1 data cache and show that the enhanced victim cache technique yield better energy-delay and energy-delay-area products. We also propose techniques that predict the hit/ miss behavior of the victim cache accesses and bypass the victim cache when a miss can be determined quickly. We report simulation results obtained from SimpleScalar/ARM modeling a representative Network Processor architecture. The simulations show that the victim cache is able to reduce the energy consumption by as much as 17.6% (8.6% on average) while reducing the execution time by as much as 8.4% (3.7% on average) for a set of representative applications.
Original language | English (US) |
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Pages (from-to) | 262-265 |
Number of pages | 4 |
Journal | Proceedings of the International Symposium on Low Power Electronics and Design |
DOIs | |
State | Published - 2003 |
Externally published | Yes |
Event | Proceedings of the 2003 International Symposium on Low Power Electronics and Design, (ISLPED'03) - Seoul, Korea, Republic of Duration: Aug 25 2003 → Aug 27 2003 |
Keywords
- Miss Detection
- Network Processors
- Victim caches
ASJC Scopus subject areas
- General Engineering