Retiming for wire pipelining in system-on-chip

Computer Science

• Communication 80%
• Computation 60%
• System-on-Chip 60%
• Experimental Result 20%
• Parallelism 20%
• Polynomial Time Algorithm 20%
• Clock Period 20%
• Pipelining 20%
• Synchronous System 20%
• Scale Integration 20%
• Longest Interconnect 20%
• Flip-Flop 20%
• Internal Structure 20%
• Design 20%

INIS

• wires 100%
• calculation methods 60%
• design 20%
• levels 20%
• algorithms 20%
• pipelines 20%
• polynomials 20%