RPack: Routability-driven packing for cluster-based FPGAs

E. Bozorgzadeh, S. Ogrenci-Memik, M. Sarrafzadeh

Research output: Chapter in Book/Report/Conference proceedingConference contribution

50 Scopus citations

Abstract

Routing tools consume a significant portion of the total design time. Considering routability at earlier steps of the CAD flow would both yield better quality and faster design process. We present a routability-driven clustering method for cluster-based FPGAs. Our method packs LUTs into logic clusters while incorporating routability metrics into a cost function. The objective is to minimize this routability cost function. Our cost function is consistently able to indicate improved routability. Our method yields up to 50% improvement over existing clustering methods in terms of the number of routing tracks required. The average improvement obtained is 16.5%. Reduction in number of tracks yields reduced routing area.

Original languageEnglish (US)
Title of host publicationProceedings of the ASP-DAC 2001
Subtitle of host publicationAsia and South Pacific Design Automation Conference 2001
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages629-634
Number of pages6
ISBN (Electronic)0780366336
DOIs
StatePublished - Jan 1 2001
EventAsia and South Pacific Design Automation Conference 2001, ASP-DAC 2001 - Yokohama, Japan
Duration: Jan 30 2001Feb 2 2001

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Volume2001-January

Other

OtherAsia and South Pacific Design Automation Conference 2001, ASP-DAC 2001
CountryJapan
CityYokohama
Period1/30/012/2/01

Keywords

  • Clustering methods
  • Computer science
  • Cost function
  • Design automation
  • Field programmable gate arrays
  • Integrated circuit interconnections
  • Logic arrays
  • Logic circuits
  • Routing
  • Table lookup

ASJC Scopus subject areas

  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

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