Run-time power estimation in high performance microprocessors

R. Joseph*, M. Martonosi

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

173 Scopus citations

Abstract

Power concerns are becoming increasingly pressing in high-performance processors. Building power-aware and even power-adaptive computer architectures requires being able to track power consumption and attribute energy consumption to the portions of the chip that are responsible for it. This paper presents the Castle project which aims to deduce the actual runtime power dissipated by different processor units on the CPU chip by leveraging existing hardware. Namely, we examine the use of hardware performance counters as proxies for power meters. We discuss which performance counters count power-relevant events, and how to estimate event counts for power-relevant events not well supported by current, commonly available performance counters. We also discuss sampling-based approaches for estimating signal transition activity within the processor. Overall, we find that these performance counters can be quite useful in providing good power apportionment estimates for programs as they run.

Original languageEnglish (US)
Title of host publicationProceedings of the International Symposium on Low Power Electronics and Design, Digest of Technical Papers
Pages135-140
Number of pages6
StatePublished - Jan 1 2001
EventInternational Symposium on Low Electronics and Design (ISLPED'01) - Huntington Beach, CA, United States
Duration: Aug 6 2001Aug 7 2001

Other

OtherInternational Symposium on Low Electronics and Design (ISLPED'01)
CountryUnited States
CityHuntington Beach, CA
Period8/6/018/7/01

ASJC Scopus subject areas

  • Engineering(all)

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