SACTA: A self-adjusting clock tree architecture for adapting to thermal-induced delay variation

Jieyi Long*, Ja Chun Ku, Seda Ogrenci Memik, Yehea Ismail

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

10 Scopus citations


Aggressive technology scaling down and low-power design techniques lead to uneven distributed power density, which translates into heat flow in the chips, causing significant temperature variations in both spatial and temporal terms. In order to mitigate the negative impacts of temperature variations on circuit timing, we propose SACTA, a self-adjusting clock tree architecture, which performs temperature-dependent dynamic clock skew scheduling to prevent timing violations in a pipelined circuit. The dynamic and adaptive features of SACTA are enabled by our proposed automatic temperature-adjustable skew buffers and temperature-insensitive skew buffers. These special delay elements are carefully tuned to ensure resilience of the entire circuit against temperature variation. To determine their configurations, we proposed an efficient and general clock tree design and optimization framework. Furthermore, we show that SACTA is applicable across a wide spectrum of circuits, including multi-V dd/Vth designs. Experimental results show that a pipeline supported by SACTA is able to prevent thermal-induced timing violations within a significantly larger range of operating temperatures (on average, the violation-free range can be enhanced by over 15°C).

Original languageEnglish (US)
Article number5282522
Pages (from-to)1323-1336
Number of pages14
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Issue number9
StatePublished - Sep 2010


  • Clock tree architecture
  • design automation
  • self-adjusting
  • variation-tolerance

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering


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