TY - GEN
T1 - SAT-based bit-flipping attack on logic encryptions
AU - Shen, Yuanqi
AU - Rezaei, Amin
AU - Zhou, Hai
N1 - Publisher Copyright:
© 2018 EDAA.
PY - 2018/4/19
Y1 - 2018/4/19
N2 - Logic encryption is a hardware security technique that uses extra key inputs to prevent unauthorized use of a circuit. With the discovery of the SAT-based attack, new encryption techniques such as SARLock and Anti-SAT are proposed, and further combined with traditional logic encryption techniques, to guarantee both high error rates and resilience to the SAT-based attack. In this paper, the SAT-based bit-flipping attack is presented. It first separates the two groups of keys via SAT-based bit-flippings, and then attacks the traditional encryption and the SAT-resilient encryption, by conventional SAT-based attack and by-passing attack, respectively. The experimental results show that the bit-flipping attack successfully returns a circuit with the correct functionality and significantly reduces the execution time compared with other advanced attacks.
AB - Logic encryption is a hardware security technique that uses extra key inputs to prevent unauthorized use of a circuit. With the discovery of the SAT-based attack, new encryption techniques such as SARLock and Anti-SAT are proposed, and further combined with traditional logic encryption techniques, to guarantee both high error rates and resilience to the SAT-based attack. In this paper, the SAT-based bit-flipping attack is presented. It first separates the two groups of keys via SAT-based bit-flippings, and then attacks the traditional encryption and the SAT-resilient encryption, by conventional SAT-based attack and by-passing attack, respectively. The experimental results show that the bit-flipping attack successfully returns a circuit with the correct functionality and significantly reduces the execution time compared with other advanced attacks.
UR - http://www.scopus.com/inward/record.url?scp=85048804030&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85048804030&partnerID=8YFLogxK
U2 - 10.23919/DATE.2018.8342086
DO - 10.23919/DATE.2018.8342086
M3 - Conference contribution
AN - SCOPUS:85048804030
T3 - Proceedings of the 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018
SP - 629
EP - 632
BT - Proceedings of the 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018
Y2 - 19 March 2018 through 23 March 2018
ER -