Abstract
Logic encryption is a hardware security technique that uses extra key inputs to prevent unauthorized use of a circuit. With the discovery of the SAT-based attack, new encryption techniques such as SARLock and Anti-SAT are proposed, and further combined with traditional logic encryption techniques, to guarantee both high error rates and resilience to the SAT-based attack. In this paper, the SAT-based bit-flipping attack is presented. It first separates the two groups of keys via SAT-based bit-flippings, and then attacks the traditional encryption and the SAT-resilient encryption, by conventional SAT-based attack and by-passing attack, respectively. The experimental results show that the bit-flipping attack successfully returns a circuit with the correct functionality and significantly reduces the execution time compared with other advanced attacks.
| Original language | English (US) |
|---|---|
| Title of host publication | Proceedings of the 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 629-632 |
| Number of pages | 4 |
| Volume | 2018-January |
| ISBN (Electronic) | 9783981926316 |
| DOIs | |
| State | Published - Apr 19 2018 |
| Event | 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018 - Dresden, Germany Duration: Mar 19 2018 → Mar 23 2018 |
Other
| Other | 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018 |
|---|---|
| Country | Germany |
| City | Dresden |
| Period | 3/19/18 → 3/23/18 |
Fingerprint
ASJC Scopus subject areas
- Safety, Risk, Reliability and Quality
- Hardware and Architecture
- Software
- Information Systems and Management
Cite this
}
SAT-based bit-flipping attack on logic encryptions. / Shen, Yuanqi; Rezaei, Amin; Zhou, Hai.
Proceedings of the 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018. Vol. 2018-January Institute of Electrical and Electronics Engineers Inc., 2018. p. 629-632.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
TY - GEN
T1 - SAT-based bit-flipping attack on logic encryptions
AU - Shen, Yuanqi
AU - Rezaei, Amin
AU - Zhou, Hai
PY - 2018/4/19
Y1 - 2018/4/19
N2 - Logic encryption is a hardware security technique that uses extra key inputs to prevent unauthorized use of a circuit. With the discovery of the SAT-based attack, new encryption techniques such as SARLock and Anti-SAT are proposed, and further combined with traditional logic encryption techniques, to guarantee both high error rates and resilience to the SAT-based attack. In this paper, the SAT-based bit-flipping attack is presented. It first separates the two groups of keys via SAT-based bit-flippings, and then attacks the traditional encryption and the SAT-resilient encryption, by conventional SAT-based attack and by-passing attack, respectively. The experimental results show that the bit-flipping attack successfully returns a circuit with the correct functionality and significantly reduces the execution time compared with other advanced attacks.
AB - Logic encryption is a hardware security technique that uses extra key inputs to prevent unauthorized use of a circuit. With the discovery of the SAT-based attack, new encryption techniques such as SARLock and Anti-SAT are proposed, and further combined with traditional logic encryption techniques, to guarantee both high error rates and resilience to the SAT-based attack. In this paper, the SAT-based bit-flipping attack is presented. It first separates the two groups of keys via SAT-based bit-flippings, and then attacks the traditional encryption and the SAT-resilient encryption, by conventional SAT-based attack and by-passing attack, respectively. The experimental results show that the bit-flipping attack successfully returns a circuit with the correct functionality and significantly reduces the execution time compared with other advanced attacks.
UR - http://www.scopus.com/inward/record.url?scp=85048804030&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85048804030&partnerID=8YFLogxK
U2 - 10.23919/DATE.2018.8342086
DO - 10.23919/DATE.2018.8342086
M3 - Conference contribution
VL - 2018-January
SP - 629
EP - 632
BT - Proceedings of the 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018
PB - Institute of Electrical and Electronics Engineers Inc.
ER -