Scaling the issue window with look-ahead latency prediction

Yongxiang Liu*, Anahita Shayesteh, Gokhan Memik, Glenn Reinman

*Corresponding author for this work

Research output: Contribution to conferencePaperpeer-review

14 Scopus citations


In contemporary out-of-order superscalar design, high IPC is mainly achieved by exposing high instruction level parallelism (ILP). Scaling issue window size can certainly provide more ILP; however, future processor scaling demands threaten to limit the size of the issue window. In this study, we propose a dynamic instruction sorting mechanism that provides more ILP without increasing the size of the issue window. In our approach, early in the pipeline, we predict how long an instruction needs to wait before it can be issued, i.e. the waiting time for its operands to be produced. Using this knowledge, the instructions are placed into a sorting structure, which allows instructions with shorter waiting times enter the issue window ahead of those instructions with longer waiting times, preventing long-waiting instructions from clogging the issue queue. The accuracy in predicting instruction waiting times directly determines the effectiveness of our sorting mechanism. While most instructions have deterministic execution latencies, predicting load execution times is more difficult due to cache misses and in-flight loads. Loads are particularly challenging since their execution time can vary significantly. In this study, we examine techniques to predict load execution time accurately, based on data reference history.

Original languageEnglish (US)
Number of pages10
StatePublished - 2004
Event2004 International Conference on Supercomputing - Saint-Malo, France
Duration: Jun 26 2004Jul 1 2004


Other2004 International Conference on Supercomputing


  • CLP
  • Instruction Sorting
  • LHT
  • MNM
  • SILO

ASJC Scopus subject areas

  • Computer Science(all)


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