Scheduling algorithms for automated synthesis of pipelined designs on FPGAs for applications described in MATLAB

Malay Haldar; Anshuman Nayak; Alok Choudhary; Prith Banerjee

doi:10.1145/354880.354893

Scheduling algorithms for automated synthesis of pipelined designs on FPGAs for applications described in MATLAB

Malay Haldar^*, Anshuman Nayak, Alok Choudhary, Prith Banerjee

^*Corresponding author for this work

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Scopus citations

Abstract

We present a high-level synthesis framework to synthesize optimized hardware on FPGAs from algorithms described in MATLAB. We focus on a framework to pipeline loops present in the input application. We present a range of scheduling algorithms to obtain the pipeline schedule and discuss their comparative strengths. The synthesized hardwares have been mapped to a Xilinx XC4028 FPGA with external memory and corresponding experimental results are included.

Original language	English (US)
Title of host publication	Proceedings of the International Conference on Compilers, Architecture and Synthesis for Embedded Systems
Publisher	Association for Computing Machinery (ACM)
Pages	85-92
Number of pages	8
ISBN (Print)	1581133383, 9781581133387
DOIs	https://doi.org/10.1145/354880.354893
State	Published - 2000
Event	Proceedings of the International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES 2000) - San Jose, CA, United States Duration: Nov 17 2000 → Nov 18 2000

Publication series

Name	Proceedings of the International Conference on Compilers, Architecture and Synthesis for Embedded Systems

Other

Other	Proceedings of the International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES 2000)
Country/Territory	United States
City	San Jose, CA
Period	11/17/00 → 11/18/00

ASJC Scopus subject areas

Engineering(all)

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10.1145/354880.354893

Cite this

Haldar, M., Nayak, A., Choudhary, A., & Banerjee, P. (2000). Scheduling algorithms for automated synthesis of pipelined designs on FPGAs for applications described in MATLAB. In Proceedings of the International Conference on Compilers, Architecture and Synthesis for Embedded Systems (pp. 85-92). (Proceedings of the International Conference on Compilers, Architecture and Synthesis for Embedded Systems). Association for Computing Machinery (ACM). https://doi.org/10.1145/354880.354893

Haldar, Malay ; Nayak, Anshuman ; Choudhary, Alok ; Banerjee, Prith. / Scheduling algorithms for automated synthesis of pipelined designs on FPGAs for applications described in MATLAB. Proceedings of the International Conference on Compilers, Architecture and Synthesis for Embedded Systems. Association for Computing Machinery (ACM), 2000. pp. 85-92 (Proceedings of the International Conference on Compilers, Architecture and Synthesis for Embedded Systems).

@inproceedings{15717491274e4fa292b02fd138ae0fcf,

title = "Scheduling algorithms for automated synthesis of pipelined designs on FPGAs for applications described in MATLAB",

abstract = "We present a high-level synthesis framework to synthesize optimized hardware on FPGAs from algorithms described in MATLAB. We focus on a framework to pipeline loops present in the input application. We present a range of scheduling algorithms to obtain the pipeline schedule and discuss their comparative strengths. The synthesized hardwares have been mapped to a Xilinx XC4028 FPGA with external memory and corresponding experimental results are included.",

author = "Malay Haldar and Anshuman Nayak and Alok Choudhary and Prith Banerjee",

year = "2000",

doi = "10.1145/354880.354893",

language = "English (US)",

isbn = "1581133383",

series = "Proceedings of the International Conference on Compilers, Architecture and Synthesis for Embedded Systems",

publisher = "Association for Computing Machinery (ACM)",

pages = "85--92",

booktitle = "Proceedings of the International Conference on Compilers, Architecture and Synthesis for Embedded Systems",

address = "United States",

note = "Proceedings of the International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES 2000) ; Conference date: 17-11-2000 Through 18-11-2000",

}

Haldar, M, Nayak, A, Choudhary, A & Banerjee, P 2000, Scheduling algorithms for automated synthesis of pipelined designs on FPGAs for applications described in MATLAB. in Proceedings of the International Conference on Compilers, Architecture and Synthesis for Embedded Systems. Proceedings of the International Conference on Compilers, Architecture and Synthesis for Embedded Systems, Association for Computing Machinery (ACM), pp. 85-92, Proceedings of the International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES 2000), San Jose, CA, United States, 11/17/00. https://doi.org/10.1145/354880.354893

Scheduling algorithms for automated synthesis of pipelined designs on FPGAs for applications described in MATLAB. / Haldar, Malay; Nayak, Anshuman; Choudhary, Alok; Banerjee, Prith.

Proceedings of the International Conference on Compilers, Architecture and Synthesis for Embedded Systems. Association for Computing Machinery (ACM), 2000. p. 85-92 (Proceedings of the International Conference on Compilers, Architecture and Synthesis for Embedded Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Scheduling algorithms for automated synthesis of pipelined designs on FPGAs for applications described in MATLAB

AU - Haldar, Malay

AU - Nayak, Anshuman

AU - Choudhary, Alok

AU - Banerjee, Prith

PY - 2000

Y1 - 2000

N2 - We present a high-level synthesis framework to synthesize optimized hardware on FPGAs from algorithms described in MATLAB. We focus on a framework to pipeline loops present in the input application. We present a range of scheduling algorithms to obtain the pipeline schedule and discuss their comparative strengths. The synthesized hardwares have been mapped to a Xilinx XC4028 FPGA with external memory and corresponding experimental results are included.

AB - We present a high-level synthesis framework to synthesize optimized hardware on FPGAs from algorithms described in MATLAB. We focus on a framework to pipeline loops present in the input application. We present a range of scheduling algorithms to obtain the pipeline schedule and discuss their comparative strengths. The synthesized hardwares have been mapped to a Xilinx XC4028 FPGA with external memory and corresponding experimental results are included.

UR - http://www.scopus.com/inward/record.url?scp=0034592334&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0034592334&partnerID=8YFLogxK

U2 - 10.1145/354880.354893

DO - 10.1145/354880.354893

M3 - Conference contribution

AN - SCOPUS:0034592334

SN - 1581133383

SN - 9781581133387

T3 - Proceedings of the International Conference on Compilers, Architecture and Synthesis for Embedded Systems

SP - 85

EP - 92

BT - Proceedings of the International Conference on Compilers, Architecture and Synthesis for Embedded Systems

PB - Association for Computing Machinery (ACM)

T2 - Proceedings of the International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES 2000)

Y2 - 17 November 2000 through 18 November 2000

ER -

Haldar M, Nayak A, Choudhary A, Banerjee P. Scheduling algorithms for automated synthesis of pipelined designs on FPGAs for applications described in MATLAB. In Proceedings of the International Conference on Compilers, Architecture and Synthesis for Embedded Systems. Association for Computing Machinery (ACM). 2000. p. 85-92. (Proceedings of the International Conference on Compilers, Architecture and Synthesis for Embedded Systems). https://doi.org/10.1145/354880.354893

Scheduling algorithms for automated synthesis of pipelined designs on FPGAs for applications described in MATLAB

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