Scheduling algorithms for automated synthesis of pipelined designs on FPGAs for applications described in MATLAB

Malay Haldar*, Anshuman Nayak, Alok Choudhary, Prith Banerjee

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Scopus citations

Abstract

We present a high-level synthesis framework to synthesize optimized hardware on FPGAs from algorithms described in MATLAB. We focus on a framework to pipeline loops present in the input application. We present a range of scheduling algorithms to obtain the pipeline schedule and discuss their comparative strengths. The synthesized hardwares have been mapped to a Xilinx XC4028 FPGA with external memory and corresponding experimental results are included.

Original languageEnglish (US)
Title of host publicationProceedings of the International Conference on Compilers, Architecture and Synthesis for Embedded Systems
PublisherAssociation for Computing Machinery (ACM)
Pages85-92
Number of pages8
ISBN (Print)1581133383, 9781581133387
DOIs
StatePublished - Jan 1 2000
EventProceedings of the International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES 2000) - San Jose, CA, United States
Duration: Nov 17 2000Nov 18 2000

Publication series

NameProceedings of the International Conference on Compilers, Architecture and Synthesis for Embedded Systems

Other

OtherProceedings of the International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES 2000)
CountryUnited States
CitySan Jose, CA
Period11/17/0011/18/00

ASJC Scopus subject areas

  • Engineering(all)

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