Selective wordline voltage boosting for caches to manage yield under process variations

Yan Pan*, Joonho Kong, Serkan Ozdemir, Gokhan Memik, Woo Chung Sung

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

25 Scopus citations

Abstract

One of the most important hurdles of technology scaling is process variations, i.e., variations in device characteristics. Process variations cause large fluctuations in performance and power consumption in the manufactured chips. In addition, these fluctuations cause reductions in the chip yields. In this work, we present an analysis of a representative high-performance processor architecture and show that the caches have the highest probability of causing yield losses under process variations. We then propose a novel selective wordline voltage boosting mechanism that aims at reducing the latency of the cache lines that are affected by process variations. We show that our approach can eliminate over 80% of the yield losses under medium level of variations, while incurring less than 1% per-access energy overhead on average and less than 4.5% area overhead.

Original languageEnglish (US)
Title of host publication2009 46th ACM/IEEE Design Automation Conference, DAC 2009
Pages57-62
Number of pages6
StatePublished - Nov 10 2009
Event2009 46th ACM/IEEE Design Automation Conference, DAC 2009 - San Francisco, CA, United States
Duration: Jul 26 2009Jul 31 2009

Publication series

NameProceedings - Design Automation Conference
ISSN (Print)0738-100X

Other

Other2009 46th ACM/IEEE Design Automation Conference, DAC 2009
Country/TerritoryUnited States
CitySan Francisco, CA
Period7/26/097/31/09

Keywords

  • Access time failure
  • Cache
  • Process variations
  • Selective wordline voltage boosting
  • Yield

ASJC Scopus subject areas

  • Computer Science Applications
  • Control and Systems Engineering
  • Electrical and Electronic Engineering
  • Modeling and Simulation

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