Sequential Logic Encryption against Model Checking Attack

Amin Rezaei, Hai Zhou

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Due to high IC design costs and emergence of countless untrusted foundries, logic encryption has been taken into consideration more than ever. In state-of-the-art logic encryption works, a lot of performance is sold to guarantee security against both the SAT-based and the removal attacks. However, the SAT-based attack cannot decrypt the sequential circuits if the scan chain is protected or if the unreachable states encryption is adopted. Instead, these security schemes can be defeated by the model checking attack that searches iteratively for different input sequences to put the activated IC to the desired reachable state. In this paper, we propose a practical logic encryption approach to defend against the model checking attack on sequential circuits. The robustness of the proposed approach is demonstrated by experiments on around fifty benchmarks.

Original languageEnglish (US)
Title of host publicationProceedings of the 2021 Design, Automation and Test in Europe, DATE 2021
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1178-1181
Number of pages4
ISBN (Electronic)9783981926354
DOIs
StatePublished - Feb 1 2021
Event2021 Design, Automation and Test in Europe Conference and Exhibition, DATE 2021 - Virtual, Online
Duration: Feb 1 2021Feb 5 2021

Publication series

NameProceedings -Design, Automation and Test in Europe, DATE
Volume2021-February
ISSN (Print)1530-1591

Conference

Conference2021 Design, Automation and Test in Europe Conference and Exhibition, DATE 2021
CityVirtual, Online
Period2/1/212/5/21

Keywords

  • Model Checking Attack
  • Sequential Encryption
  • Sequential Logic Encryption
  • Sequential Transformation

ASJC Scopus subject areas

  • Engineering(all)

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