Simultaneous routing and buffer insertion with restrictions on buffer locations

Hai Zhou*, D. F. Wong, I. Min Liu, Adnan Aziz

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

45 Scopus citations


During the routing of global interconnects, macro blocks form useful routing regions which allow wires to go through but forbid buffers to be inserted. They give restrictions on buffer locations. In this paper, we take these buffer location restrictions into consideration and solve the simultaneous maze routing and buffer insertion problem. Given a block placement defining buffer location restrictions and a pair of pins (a source and a sink), we give a polynomial time exact algorithm to find a buffered route from the source to the sink with minimum Elmore delay.

Original languageEnglish (US)
Pages (from-to)96-99
Number of pages4
JournalProceedings - Design Automation Conference
StatePublished - 1999
Event36th Annual Design Automation Conference, DAC 1999 - New Orleans, LA, USA
Duration: Jun 21 1999Jun 25 1999

ASJC Scopus subject areas

  • Hardware and Architecture
  • Control and Systems Engineering


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