Abstract
A source line sensing (SLS) scheme is presented, along with a corresponding memory core circuit architecture, for the sensing operation of magneto-electric random-access memory (MeRAM). Compared to a conventional bit-line sensing (BLS) scheme, the proposed SLS, which exploits the voltage-controlled magnetic anisotropy (VCMA) effect, applies a voltage across the magneto-electric tunnel junction (MEJ) with an opposite polarity. The SLS significantly reduces read disturbance and increases the sensing margin due to the enhanced coercivity of the bit during the read operation. Experimental data demonstrate that the thermal stability of nanoscale MEJs increases up to 2 times during the SLS operation compared with conventional BLS. An MEJ compact model based the SLS simulation shows that read disturbance improves by a factor greater than 10{}^{9} fJ/V\cdot m and the sensing margin increases up to 3 times in the MEJ with the large VCMA coefficient \left(>\text{100}\ \text{fJ}/\text{V}\cdot\text{m}\right).
Original language | English (US) |
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Article number | 7448888 |
Journal | IEEE Magnetics Letters |
Volume | 7 |
DOIs | |
State | Published - 2016 |
Funding
This work was supported in part by the NSF Nanosystems Engineering Research Center for TANMS. The authors would like to acknowledge the collaboration of this research with KACST via the CEGN
Keywords
- Spin Electronics
- magnetoelectric random access memory (MeRAM)
- magnetoelectric tunnel junction (MEJ)
- read disturbance
- thermal stability
- tunneling magnetoresistance (TMR)
- voltage controlled magnetic anisotropy (VCMA)
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials