Statistical timing yield optimization by gate sizing

Debjit Sinha*, Narendra V. Shenoy, Hai Zhou

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

20 Scopus citations


In this paper, we propose a statistical gate sizing approach to maximize the timing yield of a given circuit, under area constraints. Our approach involves statistical gate delay modeling, statistical static timing analysis, and gate sizing. Experiments performed in an industrial framework on combinational International Symposium on Circuits and Systems (ISCAS'85) and Microelectronics Center of North Carolina (MCNC) benchmarks show absolute timing yield gains of 30% on the average, over deterministic timing optimization for at most 10% area penalty. It is further shown that circuits optimized using our metric have larger timing yields than the same optimized using a worst case metric, for iso-area solutions. Finally, we present an insight into statistical properties of gate delays for a commercial 0.13-μm technology library which intuitively provides one reason why statistical timing driven optimization does better than deterministic timing driven optimization.

Original languageEnglish (US)
Article number1715350
Pages (from-to)1140-1146
Number of pages7
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Issue number10
StatePublished - Oct 2006


  • Gate sizing
  • Optimization
  • Statistical gate delay modeling
  • Statistical timing analysis
  • Timing yield
  • VLSI
  • Variability

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering


Dive into the research topics of 'Statistical timing yield optimization by gate sizing'. Together they form a unique fingerprint.

Cite this