Store-ordered streaming of shared memory

Thomas F. Wenisch*, Stephen Somogyi, Nikolaos Hardavellas, Jangwoo Kim, Chris Gniady, Anastassia Ailamaki, Babak Falsafi

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

11 Scopus citations

Abstract

Coherence misses in shared-memory multiprocessors account for a substantial fraction of execution time in many important scientific and commercial workloads. Memory streaming provides a promising solution to the coherence miss bottleneck because it improves memory level parallelism and lookahead while using on-chip resources efficiently. We observe that the order in which shared data are consumed by one processor is correlated to the order in which they were produced by another. We investigate this phenomenon and demonstrate that it can be exploited to send Store-ORDered Streams (SORDS) of shared data from producers to consumers, thereby eliminating coherent read misses. Using a trace-driven analysis of all user and OS memory references in a cache-coherent distributed shared-memory multiprocessor, we show that SORDS-based memory streaming can eliminate between 36% and 100% of all coherent read misses in scientific workloads and between 23% and 48% in online transaction processing workloads.

Original languageEnglish (US)
Title of host publication14th International Conference on Parallel Architectures and Compilation Techniques, PACT 2005
Pages75-84
Number of pages10
DOIs
StatePublished - 2005
Event14th International Conference on Parallel Architectures and Compilation Techniques, PACT 2005 - St. Louis, MO, United States
Duration: Sep 17 2005Sep 21 2005

Publication series

NameParallel Architectures and Compilation Techniques - Conference Proceedings, PACT
Volume2005
ISSN (Print)1089-795X

Other

Other14th International Conference on Parallel Architectures and Compilation Techniques, PACT 2005
Country/TerritoryUnited States
CitySt. Louis, MO
Period9/17/059/21/05

ASJC Scopus subject areas

  • Software
  • Theoretical Computer Science
  • Hardware and Architecture

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