Streaming implementation of the ZLIB decoder algorithm on an FPGA

Many new real-time system require high-speed compression and decompression solutions that provide low latency links between systems over a network interface. We describe a methodology for implementing an optimized streaming ZLIB decoder system on a Xilinx Virtex-5 FPGA board, which exploits the fine-grain parallelism in the software architecture to improve the performance. We describe a ZLIB decoder system in hardware and concrete examples of how to transform the sequential software algorithm into a highly optimized hardware implementation in RTL VHDL. Experimental results show 50x speedup in terms of cycles and 2.83x speedup in terms of time in the FPGA over the software. The ZLIB decoder was shown to operate at a rate of 1 GBit/s.