TY - GEN
T1 - ST2GPU
T2 - 58th ACM/IEEE Design Automation Conference, DAC 2021
AU - Kandiah, Vijay
AU - Gok, Ali Murat
AU - Tziantzioulis, Georgios
AU - Hardavellas, Nikos
N1 - Funding Information:
This work was partially funded by NSF awards CCF-1453853, CNS-1763743.
Publisher Copyright:
© 2021 IEEE.
PY - 2021/12/5
Y1 - 2021/12/5
N2 - Modern GPUs employ thousands of cores, yielding higher performance but also higher power consumption. To meet performance targets while staying within a reasonable power budget, designers have to make these execution cores increasingly more power efficient. One way to increase their power efficiency is to employ power-efficient adders. In this paper, we observe that consecutive arithmetic computations from the same code location are highly correlated and propose ST2 GPU, a GPU architecture that uses history-based speculative adders that produce guaranteed correct results while saving 70% of the nominal adder power. We estimate that ST2 GPU saves 21% of the GPU chip energy with practically no performance and area overheads.
AB - Modern GPUs employ thousands of cores, yielding higher performance but also higher power consumption. To meet performance targets while staying within a reasonable power budget, designers have to make these execution cores increasingly more power efficient. One way to increase their power efficiency is to employ power-efficient adders. In this paper, we observe that consecutive arithmetic computations from the same code location are highly correlated and propose ST2 GPU, a GPU architecture that uses history-based speculative adders that produce guaranteed correct results while saving 70% of the nominal adder power. We estimate that ST2 GPU saves 21% of the GPU chip energy with practically no performance and area overheads.
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U2 - 10.1109/DAC18074.2021.9586093
DO - 10.1109/DAC18074.2021.9586093
M3 - Conference contribution
AN - SCOPUS:85119419557
T3 - Proceedings - Design Automation Conference
SP - 271
EP - 276
BT - 2021 58th ACM/IEEE Design Automation Conference, DAC 2021
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 5 December 2021 through 9 December 2021
ER -