Problem statement: Nanotransistor now is one of the most promising fields in nanoelectronic in order to less energy consuming and application to create developed programmable information processors. Most of Computing and communications companies invest hundreds of millions of dollars in research funds every year to develop smaller transistors. Approach: The Junction-less side gate silicon Nano-wire transistor has been fabricated by Atomic Force Microscopy (AFM) and wet etching on p-type Silicon On Insulator (SOI) wafer. Then, we checked the characteristic and conductance trend in this device regarding to semi-classical approach by Semiconductor Probe Analyser (SPA). Results: We observe in characteristic of the device directly proportionality of the negative gate voltage and Source-Drain current. In semi classical approach, negative Gate voltage falling down the energy States of the Nano-wire between the source and the drain. The graph for positive gate voltage plotted as well to check. In other hand, the conductance will be following characteristic due to varying the gate voltage under the different drain-source voltage. Conclusion: The channel energy states are supposed to locate between two electrochemical potentials of the contacts in order to transform the charge. For the p-type channel the transform of the carriers is located in valence band and changing the positive or negative gate voltage, make the valence band energy states out of or in the area between the electrochemical potentials of the contacts causing the current reduced or increased.
- Density of state (DoS)
- Electrochemical potential
- Silicon nanowire transistor (SNWT)
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