Northwestern researchers have developed a way to use EDA software to estimate the so-called "Coupling power" of integrated circuits. By taking into consideration timing dependencies in circuits, the invention can reduce errors to estimate coupling power by as much as sixty percent (60%). The invention is the first work to take timing dependencies into consideration. Abstract It is a major challenge to minimize thermal dissipation in today's densely packed integrated circuits. One result is that increasing levels of sophistication are required to accurately predict power dissipation during the design phase. Currently available tools that predict power dissipation either ignore coupling power or fail to consider the timing-dependent power loss due to coupling capacitance effects between interconnects. Instead, current tools consider only the effective capacitance between interconnects and ground, which includes the coupling capacitance without any timing information. The invention considers relative switching activities and delays, and consideration of these timing effects enables coupling power to be accurately predicted. So, the invention uses timing information for accurate coupling power estimation, and its methods can be incorporated into EDA software. For more details on the invention, see D. Sinha, D. Khalil, H. Zhou, Y. Ismail, A Timing Dependent Power Estimation Framework Considering Coupling, Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 401-407, November 2006. Experimental results using the ISCAS'85 benchmarks demonstrate that ignoring timing dependence of coupling power can cause up to 25% error in the total dynamic power estimation, corresponding to 60% error in the coupling power estimation. So, by taking into consideration timing dependencies in circuits, the invention can reduce errors to estimate coupling power by as much as sixty percent (60%).
|State||Published - May 7 2009|